From 8efb48a6847c5cd166c561127ae6611150963ce3 Mon Sep 17 00:00:00 2001 From: Nikhil Raj Date: Fri, 19 May 2023 11:14:28 +0100 Subject: Update Doxygen docu for 23.05 Signed-off-by: Nikhil Raj Change-Id: I0a992286f14fa68fcc6e5eba31ac39fed003cbbe --- ...convert_fp16_to_fp32_workload_8cpp_source.xhtml | 176 +++++++++++++++++++++ 1 file changed, 176 insertions(+) create mode 100644 23.05/_ref_convert_fp16_to_fp32_workload_8cpp_source.xhtml (limited to '23.05/_ref_convert_fp16_to_fp32_workload_8cpp_source.xhtml') diff --git a/23.05/_ref_convert_fp16_to_fp32_workload_8cpp_source.xhtml b/23.05/_ref_convert_fp16_to_fp32_workload_8cpp_source.xhtml new file mode 100644 index 0000000000..46820bc2bb --- /dev/null +++ b/23.05/_ref_convert_fp16_to_fp32_workload_8cpp_source.xhtml @@ -0,0 +1,176 @@ + + + + + + + + + + + + + +ArmNN: src/backends/reference/workloads/RefConvertFp16ToFp32Workload.cpp Source File + + + + + + + + + + + + + + + + +
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+  23.05 +
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RefConvertFp16ToFp32Workload.cpp
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+Go to the documentation of this file.
1 //
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2 // Copyright © 2022 Arm Ltd and Contributors. All rights reserved.
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3 // SPDX-License-Identifier: MIT
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4 //
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5 
+ +
7 #include "RefWorkloadUtils.hpp"
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8 
+ +
10 
+
11 #include <Half.hpp>
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12 
+
13 namespace armnn
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14 {
+
15 
+ +
17 {
+ +
19 }
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20 
+ +
22 {
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23  WorkingMemDescriptor* workingMemDescriptor = static_cast<WorkingMemDescriptor*>(executionData.m_Data);
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24  Execute(workingMemDescriptor->m_Inputs, workingMemDescriptor->m_Outputs);
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25 }
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26 
+
27 void RefConvertFp16ToFp32Workload::Execute(std::vector<ITensorHandle*> inputs,
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28  std::vector<ITensorHandle*> outputs) const
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29 {
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30  ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefConvertFp16ToFp32Workload_Execute");
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31 
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32  const Half* const input = reinterpret_cast<const Half*>(inputs[0]->Map());
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33  float* const output = reinterpret_cast<float*>(outputs[0]->Map());
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34 
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35  unsigned int numElements = GetTensorInfo(inputs[0]).GetNumElements();
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37 }
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38 
+
39 } //namespace armnn
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+
+
const TensorInfo & GetTensorInfo(const ITensorHandle *tensorHandle)
float32 helpers
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QueueDescriptor m_Data
Definition: Workload.hpp:83
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Copyright (c) 2021 ARM Limited and Contributors.
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half_float::half Half
Definition: Half.hpp:22
+ +
#define ARMNN_SCOPED_PROFILING_EVENT(backendId, name)
Definition: Profiling.hpp:220
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unsigned int GetNumElements() const
Definition: Tensor.hpp:196
+ +
void ExecuteAsync(ExecutionData &executionData) override
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std::vector< ITensorHandle * > m_Outputs
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static void ConvertFloat16To32(const void *srcFloat16Buffer, size_t numElements, float *dstFloat32Buffer)
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@ CpuRef
CPU Execution: Reference C++ kernels.
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std::vector< ITensorHandle * > m_Inputs
+ + + + -- cgit v1.2.1