From f4019872c1134c6fcc1d6993e5746f55c1e79208 Mon Sep 17 00:00:00 2001 From: Nikhil Raj Date: Tue, 8 Mar 2022 20:01:38 +0000 Subject: IVGCVSW-6819 Fix the directory structure and broken link to latest docu Signed-off-by: Nikhil Raj Change-Id: I05b559d15faf92c76ff536719693b361316be4f3 --- 22.02/_ref_slice_workload_8cpp_source.xhtml | 134 ++++++++++++++++++++++++++++ 1 file changed, 134 insertions(+) create mode 100644 22.02/_ref_slice_workload_8cpp_source.xhtml (limited to '22.02/_ref_slice_workload_8cpp_source.xhtml') diff --git a/22.02/_ref_slice_workload_8cpp_source.xhtml b/22.02/_ref_slice_workload_8cpp_source.xhtml new file mode 100644 index 0000000000..6530c37487 --- /dev/null +++ b/22.02/_ref_slice_workload_8cpp_source.xhtml @@ -0,0 +1,134 @@ + + + + + + + + + + + + + +ArmNN: src/backends/reference/workloads/RefSliceWorkload.cpp Source File + + + + + + + + + + + + + + + + +
+
+ + + + ArmNN + + + +
+
+  22.02 +
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+
RefSliceWorkload.cpp
+
+
+Go to the documentation of this file.
1 //
2 // Copyright © 2019 Arm Ltd. All rights reserved.
3 // SPDX-License-Identifier: MIT
4 //
5 
6 #include "RefSliceWorkload.hpp"
7 
8 #include "RefWorkloadUtils.hpp"
9 #include "Slice.hpp"
10 
11 #include <Profiling.hpp>
12 
13 namespace armnn
14 {
15 
16 void RefSliceWorkload::Execute() const
17 {
18  Execute(m_Data.m_Inputs, m_Data.m_Outputs);
19 }
20 
21 void RefSliceWorkload::ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor)
22 {
23  Execute(workingMemDescriptor.m_Inputs, workingMemDescriptor.m_Outputs);
24 }
25 
26 void RefSliceWorkload::Execute(std::vector<ITensorHandle*> inputs, std::vector<ITensorHandle*> outputs) const
27 {
28  ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefSliceWorkload_Execute");
29 
30  const TensorInfo& inputInfo = GetTensorInfo(inputs[0]);
31 
32  Slice(inputInfo,
33  m_Data.m_Parameters,
34  inputs[0]->Map(),
35  outputs[0]->Map(),
36  GetDataTypeSize(inputInfo.GetDataType()));
37 }
38 
39 } // namespace armnn
RefSliceWorkload.hpp
+
armnn::Compute::CpuRef
CPU Execution: Reference C++ kernels.
+
RefWorkloadUtils.hpp
+ +
armnn::RefSliceWorkload::Execute
void Execute() const override
Definition: RefSliceWorkload.cpp:16
+
armnn::RefSliceWorkload::ExecuteAsync
void ExecuteAsync(WorkingMemDescriptor &workingMemDescriptor) override
Definition: RefSliceWorkload.cpp:21
+
armnn
Copyright (c) 2021 ARM Limited and Contributors.
Definition: 01_00_quick_start.dox:6
+ +
ARMNN_SCOPED_PROFILING_EVENT
#define ARMNN_SCOPED_PROFILING_EVENT(backendId, name)
Definition: Profiling.hpp:220
+ + + +
armnn::TensorInfo::GetDataType
DataType GetDataType() const
Definition: Tensor.hpp:198
+
armnn::QueueDescriptor::m_Outputs
std::vector< ITensorHandle * > m_Outputs
Definition: WorkloadData.hpp:27
+ +
armnn::QueueDescriptor::m_Inputs
std::vector< ITensorHandle * > m_Inputs
Definition: WorkloadData.hpp:26
+
armnn::GetTensorInfo
const TensorInfo & GetTensorInfo(const ITensorHandle *tensorHandle)
float32 helpers
Definition: RefWorkloadUtils.hpp:26
+
Profiling.hpp
+ +
Slice.hpp
+
armnn::GetDataTypeSize
constexpr unsigned int GetDataTypeSize(DataType dataType)
Definition: TypesUtils.hpp:151
+
+
+ + + + -- cgit v1.2.1