From add078b7f9a658d52ee6e8fe6771ea0517c07674 Mon Sep 17 00:00:00 2001 From: mathad01 Date: Mon, 10 May 2021 16:51:20 +0100 Subject: IVGCVSW-5908 Update 21.05 Doxygen Documents Signed-off-by: mathad01 Change-Id: I95316d4fc5f9d10185492dc835bb2411c1daea7b --- 21.05/_cl_logical_or_workload_8cpp_source.xhtml | 133 ++++++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 21.05/_cl_logical_or_workload_8cpp_source.xhtml (limited to '21.05/_cl_logical_or_workload_8cpp_source.xhtml') diff --git a/21.05/_cl_logical_or_workload_8cpp_source.xhtml b/21.05/_cl_logical_or_workload_8cpp_source.xhtml new file mode 100644 index 0000000000..7d487c671f --- /dev/null +++ b/21.05/_cl_logical_or_workload_8cpp_source.xhtml @@ -0,0 +1,133 @@ + + + + + + + + + + + + + +ArmNN: src/backends/cl/workloads/ClLogicalOrWorkload.cpp Source File + + + + + + + + + + + + + + + + +
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ClLogicalOrWorkload.cpp
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1 //
2 // Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
3 // SPDX-License-Identifier: MIT
4 //
5 
6 #include "ClLogicalOrWorkload.hpp"
7 
8 #include "ClWorkloadUtils.hpp"
9 
10 #include <armnn/utility/PolymorphicDowncast.hpp>
11 
12 #include <aclCommon/ArmComputeTensorUtils.hpp>
13 
14 #include <cl/ClTensorHandle.hpp>
15 
16 namespace armnn
17 {
18 using namespace armcomputetensorutils;
19 
20 arm_compute::Status ClLogicalOrWorkloadValidate(const TensorInfo& input0,
21  const TensorInfo& input1,
22  const TensorInfo& output)
23 {
24  const arm_compute::TensorInfo aclInputInfo0 = BuildArmComputeTensorInfo(input0);
25  const arm_compute::TensorInfo aclInputInfo1 = BuildArmComputeTensorInfo(input1);
26  const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output);
27 
28  const arm_compute::Status aclStatus = arm_compute::CLLogicalOr::validate(&aclInputInfo0,
29  &aclInputInfo1,
30  &aclOutputInfo);
31  return aclStatus;
32 }
33 
34 ClLogicalOrWorkload::ClLogicalOrWorkload(const LogicalBinaryQueueDescriptor& descriptor,
35  const WorkloadInfo& info,
36  const arm_compute::CLCompileContext& clCompileContext)
37  : BaseWorkload<LogicalBinaryQueueDescriptor>(descriptor, info)
38 {
39  m_Data.ValidateInputsOutputs("ClLogicalOrWorkload", 2, 1);
40 
41  arm_compute::ICLTensor& input0 = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor();
42  arm_compute::ICLTensor& input1 = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[1])->GetTensor();
43  arm_compute::ICLTensor& output = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor();
44 
45  m_LogicalOrLayer.configure(clCompileContext, &input0, &input1, &output);
46 }
47 
48 void ClLogicalOrWorkload::Execute() const
49 {
50  ARMNN_SCOPED_PROFILING_EVENT_CL("ClLogicalOrWorkload_Execute");
51  m_LogicalOrLayer.run();
52 }
53 
54 } // namespace armnn
armnn::ClLogicalOrWorkloadValidate
arm_compute::Status ClLogicalOrWorkloadValidate(const TensorInfo &input0, const TensorInfo &input1, const TensorInfo &output)
Definition: ClLogicalOrWorkload.cpp:20
+ +
ClLogicalOrWorkload.hpp
+
ARMNN_SCOPED_PROFILING_EVENT_CL
#define ARMNN_SCOPED_PROFILING_EVENT_CL(name)
Definition: ClWorkloadUtils.hpp:20
+
ArmComputeTensorUtils.hpp
+
armnn::QueueDescriptor::ValidateInputsOutputs
void ValidateInputsOutputs(const std::string &descName, unsigned int numExpectedIn, unsigned int numExpectedOut) const
Definition: WorkloadData.cpp:459
+
armnn
Copyright (c) 2021 ARM Limited and Contributors.
Definition: 01_00_software_tools.dox:6
+
PolymorphicDowncast.hpp
+ +
armnn::ClLogicalOrWorkload::Execute
virtual void Execute() const override
Definition: ClLogicalOrWorkload.cpp:48
+ +
armnn::Status
Status
enumeration
Definition: Types.hpp:30
+ +
ClTensorHandle.hpp
+
armnn::QueueDescriptor::m_Outputs
std::vector< ITensorHandle * > m_Outputs
Definition: WorkloadData.hpp:31
+ +
armnn::ClLogicalOrWorkload::ClLogicalOrWorkload
ClLogicalOrWorkload(const LogicalBinaryQueueDescriptor &descriptor, const WorkloadInfo &info, const arm_compute::CLCompileContext &clCompileContext)
Definition: ClLogicalOrWorkload.cpp:34
+
armnn::WorkloadInfo
Contains information about inputs and outputs to a layer.
Definition: WorkloadInfo.hpp:16
+
armnn::QueueDescriptor::m_Inputs
std::vector< ITensorHandle * > m_Inputs
Definition: WorkloadData.hpp:30
+
ClWorkloadUtils.hpp
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