From fd627ffaec8fd8801d980b4c91ee7c0607ab6aaf Mon Sep 17 00:00:00 2001 From: Jan Eilers Date: Thu, 25 Feb 2021 17:44:00 +0000 Subject: IVGCVSW-5687 Update Doxygen Docu * Update Doxygen Documentation for 21.02 release Signed-off-by: Jan Eilers Change-Id: I9ed2f9caab038836ea99d7b378d7899fe431a4e5 --- ...nspose_convolution2d_workload_8cpp_source.xhtml | 138 +++++++++++++++++++++ 1 file changed, 138 insertions(+) create mode 100644 21.02/_ref_transpose_convolution2d_workload_8cpp_source.xhtml (limited to '21.02/_ref_transpose_convolution2d_workload_8cpp_source.xhtml') diff --git a/21.02/_ref_transpose_convolution2d_workload_8cpp_source.xhtml b/21.02/_ref_transpose_convolution2d_workload_8cpp_source.xhtml new file mode 100644 index 0000000000..6ae63a5d2b --- /dev/null +++ b/21.02/_ref_transpose_convolution2d_workload_8cpp_source.xhtml @@ -0,0 +1,138 @@ + + + + + + + + + + + + + +ArmNN: src/backends/reference/workloads/RefTransposeConvolution2dWorkload.cpp Source File + + + + + + + + + + + + + + + + +
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RefTransposeConvolution2dWorkload.cpp
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+Go to the documentation of this file.
1 //
2 // Copyright © 2017 Arm Ltd. All rights reserved.
3 // SPDX-License-Identifier: MIT
4 //
5 
6 #include "RefTransposeConvolution2dWorkload.hpp"
7 
8 #include "RefWorkloadUtils.hpp"
9 #include "TransposeConvolution2d.hpp"
10 
11 #include <Profiling.hpp>
12 
13 namespace armnn
14 {
15 
16 RefTransposeConvolution2dWorkload::RefTransposeConvolution2dWorkload(
17  const TransposeConvolution2dQueueDescriptor& descriptor, const WorkloadInfo& info) :
18  BaseWorkload<TransposeConvolution2dQueueDescriptor>(descriptor, info)
19 {
20  // set up weights decoder
21  m_Weights = std::make_unique<ScopedCpuTensorHandle>(*(descriptor.m_Weight));
22  const TensorInfo& weightsInfo = m_Weights->GetTensorInfo();
23 
24  m_WeightsDecoder = MakeDecoder<float>(weightsInfo, m_Weights->Map(true));
25  m_WeightsShape = weightsInfo.GetShape();
26 
27  // set up biases decoder
28  if (descriptor.m_Parameters.m_BiasEnabled)
29  {
30  m_Biases = std::make_unique<ScopedCpuTensorHandle>(*(descriptor.m_Bias));
31  const TensorInfo& biasesInfo = m_Biases->GetTensorInfo();
32  m_BiasesDecoder = MakeDecoder<float>(biasesInfo, m_Biases->Map(true));
33  }
34 }
35 
36 void RefTransposeConvolution2dWorkload::PostAllocationConfigure()
37 {
38  // set up input decoder
39  const ITensorHandle* input = m_Data.m_Inputs[0];
40  const TensorInfo& inputInfo = GetTensorInfo(input);
41 
42  m_InputShape = inputInfo.GetShape();
43  m_InputDecoder = MakeDecoder<float>(inputInfo);
44 
45  // set up output encoder
46  ITensorHandle* output = m_Data.m_Outputs[0];
47  const TensorInfo& outputInfo = GetTensorInfo(output);
48 
49  m_OutputShape = outputInfo.GetShape();
50  m_OutputEncoder = MakeEncoder<float>(outputInfo);
51 }
52 
53 void RefTransposeConvolution2dWorkload::Execute() const
54 {
55  ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefTransposeConvolution2dWorkload_Execute");
56 
57  m_InputDecoder->Reset(m_Data.m_Inputs[0]->Map());
58  m_OutputEncoder->Reset(m_Data.m_Outputs[0]->Map());
59 
60  TransposeConvolution2dImpl(m_Data.m_Parameters,
61  m_InputShape,
62  *m_InputDecoder,
63  m_OutputShape,
64  *m_OutputEncoder,
65  m_WeightsShape,
66  *m_WeightsDecoder,
67  m_BiasesDecoder.get());
68 }
69 
70 } // namespace armnn
armnn::TensorInfo::GetShape
const TensorShape & GetShape() const
Definition: Tensor.hpp:187
+
armnn::Compute::CpuRef
CPU Execution: Reference C++ kernels.
+
RefWorkloadUtils.hpp
+ + + +
armnn::TransposeConvolution2dDescriptor::m_BiasEnabled
bool m_BiasEnabled
Enable/disable bias.
Definition: Descriptors.hpp:1254
+
armnn::BaseWorkload< TransposeConvolution2dQueueDescriptor >::m_Data
const TransposeConvolution2dQueueDescriptor m_Data
Definition: Workload.hpp:46
+
armnn::TransposeConvolution2dImpl
void TransposeConvolution2dImpl(const TransposeConvolution2dDescriptor &descriptor, const TensorShape &inputShape, Decoder< float > &inputDecoder, const TensorShape &outputShape, Encoder< float > &outputEncoder, const TensorShape &weightsShape, Decoder< float > &weightsDecoder, Decoder< float > *biasesDecoder)
Definition: TransposeConvolution2d.cpp:15
+
armnn
Copyright (c) 2021 ARM Limited and Contributors.
Definition: 01_00_software_tools.dox:6
+ + +
ARMNN_SCOPED_PROFILING_EVENT
#define ARMNN_SCOPED_PROFILING_EVENT(backendId, name)
Definition: Profiling.hpp:173
+
TransposeConvolution2d.hpp
+ + + +
armnn::RefTransposeConvolution2dWorkload::RefTransposeConvolution2dWorkload
RefTransposeConvolution2dWorkload(const TransposeConvolution2dQueueDescriptor &descriptor, const WorkloadInfo &info)
Definition: RefTransposeConvolution2dWorkload.cpp:16
+
RefTransposeConvolution2dWorkload.hpp
+ +
armnn::QueueDescriptor::m_Outputs
std::vector< ITensorHandle * > m_Outputs
Definition: WorkloadData.hpp:31
+
armnn::WorkloadInfo
Contains information about inputs and outputs to a layer.
Definition: WorkloadInfo.hpp:16
+
armnn::QueueDescriptor::m_Inputs
std::vector< ITensorHandle * > m_Inputs
Definition: WorkloadData.hpp:30
+
armnn::GetTensorInfo
const TensorInfo & GetTensorInfo(const ITensorHandle *tensorHandle)
float32 helpers
Definition: RefWorkloadUtils.hpp:26
+
Profiling.hpp
+
+
+ + + + -- cgit v1.2.1