From fd627ffaec8fd8801d980b4c91ee7c0607ab6aaf Mon Sep 17 00:00:00 2001 From: Jan Eilers Date: Thu, 25 Feb 2021 17:44:00 +0000 Subject: IVGCVSW-5687 Update Doxygen Docu * Update Doxygen Documentation for 21.02 release Signed-off-by: Jan Eilers Change-Id: I9ed2f9caab038836ea99d7b378d7899fe431a4e5 --- 21.02/_ref_prelu_workload_8cpp_source.xhtml | 130 ++++++++++++++++++++++++++++ 1 file changed, 130 insertions(+) create mode 100644 21.02/_ref_prelu_workload_8cpp_source.xhtml (limited to '21.02/_ref_prelu_workload_8cpp_source.xhtml') diff --git a/21.02/_ref_prelu_workload_8cpp_source.xhtml b/21.02/_ref_prelu_workload_8cpp_source.xhtml new file mode 100644 index 0000000000..bb741262f6 --- /dev/null +++ b/21.02/_ref_prelu_workload_8cpp_source.xhtml @@ -0,0 +1,130 @@ + + + + + + + + + + + + + +ArmNN: src/backends/reference/workloads/RefPreluWorkload.cpp Source File + + + + + + + + + + + + + + + + +
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RefPreluWorkload.cpp
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+Go to the documentation of this file.
1 //
2 // Copyright © 2017 Arm Ltd. All rights reserved.
3 // SPDX-License-Identifier: MIT
4 //
5 
6 #include "RefPreluWorkload.hpp"
7 
8 #include "RefWorkloadUtils.hpp"
9 #include "PreluImpl.hpp"
10 
11 #include <Profiling.hpp>
12 
13 namespace armnn
14 {
15 
16 RefPreluWorkload::RefPreluWorkload(const PreluQueueDescriptor& descriptor,
17  const WorkloadInfo& info)
18  : BaseWorkload(descriptor, info)
19 {}
20 
21 void RefPreluWorkload::Execute() const
22 {
23  ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefPreluWorkload_Execute");
24 
25  std::unique_ptr<Decoder<float>> inputDecoder = MakeDecoder<float>(GetTensorInfo(m_Data.m_Inputs[0]),
26  m_Data.m_Inputs[0]->Map());
27  std::unique_ptr<Decoder<float>> alphaDecoder = MakeDecoder<float>(GetTensorInfo(m_Data.m_Inputs[1]),
28  m_Data.m_Inputs[1]->Map());
29  std::unique_ptr<Encoder<float>> outputEncoder = MakeEncoder<float>(GetTensorInfo(m_Data.m_Outputs[0]),
30  m_Data.m_Outputs[0]->Map());
31 
32  PreluImpl(m_Data, *inputDecoder, *alphaDecoder, *outputEncoder);
33 }
34 
35 } // namespace armnn
armnn::Compute::CpuRef
CPU Execution: Reference C++ kernels.
+
RefWorkloadUtils.hpp
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armnn::BaseWorkload< PreluQueueDescriptor >::m_Data
const PreluQueueDescriptor m_Data
Definition: Workload.hpp:46
+
RefPreluWorkload.hpp
+
armnn
Copyright (c) 2021 ARM Limited and Contributors.
Definition: 01_00_software_tools.dox:6
+ +
armnn::PreluImpl
void PreluImpl(const PreluQueueDescriptor &data, Decoder< float > &inputData, Decoder< float > &alphaData, Encoder< float > &outputData)
Definition: PreluImpl.cpp:13
+
ARMNN_SCOPED_PROFILING_EVENT
#define ARMNN_SCOPED_PROFILING_EVENT(backendId, name)
Definition: Profiling.hpp:173
+
armnn::RefPreluWorkload::Execute
virtual void Execute() const override
Definition: RefPreluWorkload.cpp:21
+ +
armnn::QueueDescriptor::m_Outputs
std::vector< ITensorHandle * > m_Outputs
Definition: WorkloadData.hpp:31
+
armnn::RefPreluWorkload::RefPreluWorkload
RefPreluWorkload(const PreluQueueDescriptor &descriptor, const WorkloadInfo &info)
Definition: RefPreluWorkload.cpp:16
+
armnn::WorkloadInfo
Contains information about inputs and outputs to a layer.
Definition: WorkloadInfo.hpp:16
+
PreluImpl.hpp
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armnn::QueueDescriptor::m_Inputs
std::vector< ITensorHandle * > m_Inputs
Definition: WorkloadData.hpp:30
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armnn::GetTensorInfo
const TensorInfo & GetTensorInfo(const ITensorHandle *tensorHandle)
float32 helpers
Definition: RefWorkloadUtils.hpp:26
+
Profiling.hpp
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+
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