patch/21.02/_ref_convolution2d_workload_8cpp_source.xhtml

 //
 // Copyright © 2017 Arm Ltd. All rights reserved.
 // SPDX-License-Identifier: MIT
 //

 #include "RefConvolution2dWorkload.hpp"

 #include "ConvImpl.hpp"
 #include "RefWorkloadUtils.hpp"

 #include "Profiling.hpp"

 namespace armnn
 {
 RefConvolution2dWorkload::RefConvolution2dWorkload(
         const Convolution2dQueueDescriptor& descriptor, const WorkloadInfo& info)
         : BaseWorkload<Convolution2dQueueDescriptor>(descriptor, info)
 {
     m_Weight = std::make_unique<ScopedCpuTensorHandle>(*(descriptor.m_Weight));
     const TensorInfo& rFilterInfo = m_Weight->GetTensorInfo();

     m_FilterShape = rFilterInfo.GetShape();
     m_FilterDecoder = MakeDecoder<float>(rFilterInfo, m_Weight.get()->Map(true));

     if (descriptor.m_Parameters.m_BiasEnabled)
     {
         m_Bias = std::make_unique<ScopedCpuTensorHandle>(*(descriptor.m_Bias));
         const TensorInfo& biasInfo = m_Bias->GetTensorInfo();
         m_BiasDecoder = MakeDecoder<float>(biasInfo, m_Bias->Map(true));
     }
 }

 void RefConvolution2dWorkload::PostAllocationConfigure()
 {
     const TensorInfo& inputInfo = GetTensorInfo(m_Data.m_Inputs[0]);
     m_InputShape = inputInfo.GetShape();
     m_InputDecoder = MakeDecoder<float>(inputInfo);

     const TensorInfo& outputInfo = GetTensorInfo(m_Data.m_Outputs[0]);
     m_OutputShape = outputInfo.GetShape();
     m_OutputEncoder = MakeEncoder<float>(outputInfo);
 }

 void RefConvolution2dWorkload::Execute() const {
     ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefConvolution2dWorkload_Execute");

     m_InputDecoder->Reset(m_Data.m_Inputs[0]->Map());
     m_OutputEncoder->Reset(m_Data.m_Outputs[0]->Map());

     Convolve(m_InputShape, *m_InputDecoder, m_OutputShape, *m_OutputEncoder, m_FilterShape,
              *m_FilterDecoder, m_Data.m_Parameters.m_BiasEnabled, m_BiasDecoder.get(),
              m_Data.m_Parameters.m_DataLayout, m_Data.m_Parameters.m_PadTop, m_Data.m_Parameters.m_PadLeft,
              m_Data.m_Parameters.m_StrideX, m_Data.m_Parameters.m_StrideY,
              m_Data.m_Parameters.m_DilationX, m_Data.m_Parameters.m_DilationY);
 }

 } //namespace armnn
armnn::Convolution2dDescriptor::m_BiasEnabled
bool m_BiasEnabled
Enable/disable bias.
Definition: Descriptors.hpp:454

+armnn::Convolution2dQueueDescriptor::m_Bias
const ConstCpuTensorHandle * m_Bias
Definition: WorkloadData.hpp:201

+armnn::Convolution2dDescriptor::m_DataLayout
DataLayout m_DataLayout
The data layout to be used (NCHW, NHWC).
Definition: Descriptors.hpp:456

+armnn::TensorInfo::GetShape
const TensorShape & GetShape() const
Definition: Tensor.hpp:187

+armnn::Compute::CpuRef
CPU Execution: Reference C++ kernels.

+armnn::RefConvolution2dWorkload::PostAllocationConfigure
void PostAllocationConfigure() override
Definition: RefConvolution2dWorkload.cpp:33

+RefWorkloadUtils.hpp

+armnn::TensorInfo
Definition: Tensor.hpp:152

+RefConvolution2dWorkload.hpp

+armnn::BaseWorkload< Convolution2dQueueDescriptor >::m_Data
const Convolution2dQueueDescriptor m_Data
Definition: Workload.hpp:46

+armnn
Copyright (c) 2021 ARM Limited and Contributors.
Definition: 01_00_software_tools.dox:6

+ConvImpl.hpp

+armnn::Convolution2dDescriptor::m_DilationY
uint32_t m_DilationY
Dilation along y axis.
Definition: Descriptors.hpp:452

+armnn::QueueDescriptorWithParameters::m_Parameters
LayerDescriptor m_Parameters
Definition: WorkloadData.hpp:57

+ARMNN_SCOPED_PROFILING_EVENT
#define ARMNN_SCOPED_PROFILING_EVENT(backendId, name)
Definition: Profiling.hpp:173

+armnn::Convolution2dDescriptor::m_PadTop
uint32_t m_PadTop
Padding top value in the height dimension.
Definition: Descriptors.hpp:442

+armnn::Convolution2dDescriptor::m_StrideX
uint32_t m_StrideX
Stride value when proceeding through input for the width dimension.
Definition: Descriptors.hpp:446

+armnn::RefConvolution2dWorkload::RefConvolution2dWorkload
RefConvolution2dWorkload(const Convolution2dQueueDescriptor &descriptor, const WorkloadInfo &info)
Definition: RefConvolution2dWorkload.cpp:15

+armnn::BaseWorkload
Definition: Workload.hpp:28

+armnn::Convolve
void Convolve(const TensorShape &rInputShape, Decoder< float > &rInputDecoder, const TensorShape &rOutputShape, Encoder< float > &rOutputEncoder, const TensorShape &rFilterShape, Decoder< float > &rFilterDecoder, bool biasEnabled, Decoder< float > *pBiasDecoder, DataLayout dataLayout, unsigned int paddingTop, unsigned int paddingLeft, unsigned int xStride, unsigned int yStride, unsigned int xDilation, unsigned int yDilation, bool depthwise)
Definition: ConvImpl.cpp:71

+armnn::Convolution2dQueueDescriptor::m_Weight
const ConstCpuTensorHandle * m_Weight
Definition: WorkloadData.hpp:200

+armnn::Convolution2dDescriptor::m_StrideY
uint32_t m_StrideY
Stride value when proceeding through input for the height dimension.
Definition: Descriptors.hpp:448

+armnn::Convolution2dQueueDescriptor
Definition: WorkloadData.hpp:192

+armnn::Convolution2dDescriptor::m_DilationX
uint32_t m_DilationX
Dilation along x axis.
Definition: Descriptors.hpp:450

+armnn::QueueDescriptor::m_Outputs
std::vector< ITensorHandle * > m_Outputs
Definition: WorkloadData.hpp:31

+armnn::RefConvolution2dWorkload::Execute
virtual void Execute() const override
Definition: RefConvolution2dWorkload.cpp:44

+armnn::WorkloadInfo
Contains information about inputs and outputs to a layer.
Definition: WorkloadInfo.hpp:16

+armnn::QueueDescriptor::m_Inputs
std::vector< ITensorHandle * > m_Inputs
Definition: WorkloadData.hpp:30

+armnn::GetTensorInfo
const TensorInfo & GetTensorInfo(const ITensorHandle *tensorHandle)
float32 helpers
Definition: RefWorkloadUtils.hpp:26

+Profiling.hpp

+armnn::Convolution2dDescriptor::m_PadLeft
uint32_t m_PadLeft
Padding left value in the width dimension.
Definition: Descriptors.hpp:438

+