From fb14ebbd68e04876809145296af96f6f41857418 Mon Sep 17 00:00:00 2001 From: James Ward Date: Thu, 26 Nov 2020 11:08:12 +0000 Subject: IVGCVSW-5348 Update Doxygen Docu * Update Doxygen Documentation for 20.11 release Signed-off-by: James Ward Change-Id: Ib47edac7923a642a277b1169d1085e5622021dc0 --- 20.11/_cl_logical_not_workload_8cpp_source.xhtml | 133 +++++++++++++++++++++++ 1 file changed, 133 insertions(+) create mode 100644 20.11/_cl_logical_not_workload_8cpp_source.xhtml (limited to '20.11/_cl_logical_not_workload_8cpp_source.xhtml') diff --git a/20.11/_cl_logical_not_workload_8cpp_source.xhtml b/20.11/_cl_logical_not_workload_8cpp_source.xhtml new file mode 100644 index 0000000000..e7d6723d49 --- /dev/null +++ b/20.11/_cl_logical_not_workload_8cpp_source.xhtml @@ -0,0 +1,133 @@ + + + + + + + + + + + + + +ArmNN: src/backends/cl/workloads/ClLogicalNotWorkload.cpp Source File + + + + + + + + + + + + + + + + +
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ClLogicalNotWorkload.cpp
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1 //
2 // Copyright © 2020 Arm Ltd and Contributors. All rights reserved.
3 // SPDX-License-Identifier: MIT
4 //
5 
6 #include "ClLogicalNotWorkload.hpp"
7 
8 #include "ClWorkloadUtils.hpp"
9 
10 #include <armnn/utility/PolymorphicDowncast.hpp>
11 
12 #include <aclCommon/ArmComputeTensorUtils.hpp>
13 
14 #include <cl/ClTensorHandle.hpp>
15 
16 namespace armnn
17 {
18 using namespace armcomputetensorutils;
19 
20 arm_compute::Status ClLogicalNotWorkloadValidate(const TensorInfo& input,
21  const TensorInfo& output)
22 {
23  const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input);
24  const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output);
25 
26  const arm_compute::Status aclStatus = arm_compute::CLLogicalNot::validate(&aclInputInfo,
27  &aclOutputInfo);
28  return aclStatus;
29 }
30 
31 ClLogicalNotWorkload::ClLogicalNotWorkload(const ElementwiseUnaryQueueDescriptor& descriptor,
32  const WorkloadInfo& info)
33  : BaseWorkload<ElementwiseUnaryQueueDescriptor>(descriptor, info)
34 {
35  m_Data.ValidateInputsOutputs("ClLogicalNotWorkload", 1, 1);
36 
37  arm_compute::ICLTensor& input = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor();
38  arm_compute::ICLTensor& output = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor();
39 
40  m_LogicalNotLayer.configure(&input, &output);
41 }
42 
43 void ClLogicalNotWorkload::Execute() const
44 {
45  ARMNN_SCOPED_PROFILING_EVENT_CL("ClLogicalNotWorkload_Execute");
46  m_LogicalNotLayer.run();
47 }
48 
49 } // namespace armnn
+
ARMNN_SCOPED_PROFILING_EVENT_CL
#define ARMNN_SCOPED_PROFILING_EVENT_CL(name)
Definition: ClWorkloadUtils.hpp:20
+
armnn::BaseWorkload< ElementwiseUnaryQueueDescriptor >::m_Data
const ElementwiseUnaryQueueDescriptor m_Data
Definition: Workload.hpp:46
+
armnn::ClLogicalNotWorkload::Execute
virtual void Execute() const override
Definition: ClLogicalNotWorkload.cpp:43
+
armnn::ClLogicalNotWorkload::ClLogicalNotWorkload
ClLogicalNotWorkload(const ElementwiseUnaryQueueDescriptor &descriptor, const WorkloadInfo &info)
Definition: ClLogicalNotWorkload.cpp:31
+
ArmComputeTensorUtils.hpp
+
armnn::QueueDescriptor::ValidateInputsOutputs
void ValidateInputsOutputs(const std::string &descName, unsigned int numExpectedIn, unsigned int numExpectedOut) const
Definition: WorkloadData.cpp:460
+
armnn
Copyright (c) 2020 ARM Limited.
Definition: 00_introduction.dox:25
+
PolymorphicDowncast.hpp
+
armnn::ClLogicalNotWorkloadValidate
arm_compute::Status ClLogicalNotWorkloadValidate(const TensorInfo &input, const TensorInfo &output)
Definition: ClLogicalNotWorkload.cpp:20
+ +
armnn::Status
Status
enumeration
Definition: Types.hpp:26
+
ClTensorHandle.hpp
+
armnn::QueueDescriptor::m_Outputs
std::vector< ITensorHandle * > m_Outputs
Definition: WorkloadData.hpp:31
+ +
armnn::WorkloadInfo
Contains information about inputs and outputs to a layer.
Definition: WorkloadInfo.hpp:16
+
armnn::QueueDescriptor::m_Inputs
std::vector< ITensorHandle * > m_Inputs
Definition: WorkloadData.hpp:30
+
ClWorkloadUtils.hpp
+ +
ClLogicalNotWorkload.hpp
+
+
+ + + + -- cgit v1.2.1