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2024-04-24IVGCVSW-8602 Move ComputeSplitAxis() to backendsCommon/WorkloadUtilsTeresa Charlin
* Use ComputeSplitAxis in SplitOperator in tosaCommon mappings * Fix TosaRef split tests, that were missing outputInfos Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: Ib577eacdc6399242f37d25494e208aa56db6334c
2024-04-24IVGCVSW-8205 For leakyRelu, add TosaRefEndToEndTests and Fp16 in mappingsTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: I70f81d17b696c30bf7a06491281184c4ddb8afc1
2024-04-23IVGCVSW-8294 Fix quantized Conv2d TOSA mappingJohn Mcloughlin
* TosaConv2d * TosaQuantization * TosaRescale Signed-off-by: John Mcloughlin <john.mcloughlin@arm.com> Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I6c7ceca1f7df62896b41a84e6a6448afd8c32b74
2024-04-19IVGCVSW-8314 Add Boolean data type to Debug layer support.Colm Donelan
Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: Ie2054393188c6099ecee2e09b7008860b9a7178c
2024-04-18IVGCVSW-8314 Broadcast handling for Comparison layer is inconsistent.Colm Donelan
* Added Comparison and LogicalBinary to AddBroadcastReshapeLayer optimization. Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: I4f4bafb961daf63a733be9a1f17067fd246607ad
2024-04-17MLCE-1248 Removing limitations on zero scale value in quantization.Colm Donelan
Currently Arm NN will fail to load models containing quantization scale value of zero. Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: Ifefcee1279b8667da63d1aa7d42e5d44875f9fbe
2024-04-11IVGCVSW-8165: Update TOSA Common and TosaRef to use TOSA v0.80Teresa Charlin
* Keep the order of the operators in TosaRef, so that const ops go first * Remove IsLayerSupportedTosaReferenceConstantUnsupported and open ticket in MLTOSA Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ifaa6c26dd8ad7d531f1691320d8c731956b910aa
2024-04-09IVGCVSW-8298 Fix failing fsrcnn testNikhil Raj
Change-Id: I03c26ab763ec306a6efe31f9b4e0b1c058589bf7 Signed-off-by: Nikhil Raj <nikhil.raj@arm.com>
2024-03-28Revert "IVGCVSW-8298 Fix FSRCNN CI Failure"TeresaARM
This reverts commit 518a1e4a438f47267235cff450d03efc8e7599d8. Reason for revert: <Nightly test failing> Change-Id: Ie595d1831a8391a1c9624beced4bae37898438a7
2024-03-28IVGCVSW-8298 Fix FSRCNN CI FailureDeclan-ARM
* Skip inference if profiling is set to output details only Signed-off-by: Declan-ARM <decmce01@arm.com> Change-Id: I9f35d8b1237bfa66790322a40f7ae6d09bbf6eb1
2024-03-15Remove use of `std::clamp`Declan-ARM
* Introduced in IVGCVSW-7853 (causes issues with older compilers) Signed-off-by: Declan-ARM <decmce01@arm.com> Change-Id: I945b7be5e0e8fe47c8d4859d1db40b5130392363
2024-03-14Syntax change to allow building on older compilers (ReduceLayer)Kevin May
Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: If02101d881bb7c937e858e464a043d849ac40ba9
2024-03-14Syntax change to allow building on older compilersKevin May
Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: I7148c25679a8a919c6138df6b23d0129e8ddd0a5
2024-03-13IVGCVSW-7853 Assert audit and removalDeclan-ARM
* src/armnn * src/armnn/layers Signed-off-by: Declan-ARM <decmce01@arm.com> Change-Id: Ic78cbbb59e90fbb15f893205a358c45264243721
2024-03-12IVGCVSW-8230 Add ScatterNd to Serializer and DeserializerKevin May
* Added parsing functions to the serializer and deserializer * Added ScatterNd and its Descriptor to the ArmnnSchema.fbs * Added Unittest for Serializer and Deserializer Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: I1ed674dc32d2e2d0d84dca4c7018984ea367ea50
2024-03-12IVGCVSW-8233 ScatterNd End to End tests addedTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Id89233954dd8da600c2f82e718df849b098c8af4
2024-03-12IVGCVSW-8231 ScatterNd added to TFLite parserTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I5b87304319f5e83e8eba9cb2d934fc4a6aebe85b
2024-03-08IVGCVSW-8299 Optimisation to replace Max + Min with Bounded ReluTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I0774a9580710350bd0a959cf68dfe057f52e4330
2024-02-29IVGCVSW-8212 Bug Fix: AddMulAdd optimization missing check on second ADDTeresa Charlin
* Failures was: MultiplicationQueueDescriptor: Tensors input_0 & input_1 must have the same number of dimensions in order to be broadcasted * When trying to apply AddMulAdd, Mul dimensions were being collapsed before checking the second ADD. * If the second ADD determined that fusion cannot happened MUL should have not been collapse. Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I6dda131c424e1bf7b22fff40c5bef8977f073b24
2024-02-28IVGCVSW-8229 & IVGCVSW-8237 ScatterNd: Front end and reference implementationTianle Cheng
(scatter_nd, scatter_nd_add, and scatter_nd_update, scatter_nd_sub, scatter_nd_min, scatter_nd_max, scatter_nd_mul) * Front end support for ScatterNd added. * Reference implementation for ScatterNd added. * Unit tests added. Signed-off-by: Tianle Cheng <tianle.cheng@arm.com> Change-Id: I30da9056d9b03ca9b5fb8d09987341128badbcf4
2024-02-28IVGCVSW-8172 Add macOS support to build tool setupTracy Narine
* Updates build rules for platform * Failing unit tests excluded (dynamic backends, profiling) * install-packages.sh generates manual setup information Signed-off-by: Tracy Narine <tracy.narine@arm.com> Change-Id: I2d3d434aa615a8796c0cb94cd5b9c35a5acfd148
2024-02-22IVGCVSW-7854 Remove/rewrite asserts in the backends unit tests.Colm Donelan
* Replace calls to ARMNN_ASSERT with DOCTEST CHECK. Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: I8904d169b2099d57a344e319b2f14cf5d8392ae8
2024-02-21IVGCVSW-7854 Remove/rewrite asserts in the backends.Colm Donelan
* Identify usages of ARMNN_ASSERT that should be proper exceptions. * Change ARMNN_ASSERT in Doctests to CHECK. * Verify any remaining assertions are reasonable. Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: Ifd1f2a5a4bb60135e8654305035ec70e09c4dc2d
2024-02-14Minor adjustment to the commit for MLCE-1165Tracy Narine
* Rewrote constexpr check to avoid a compile error Signed-off-by: Tracy Narine <tracy.narine@arm.com> Change-Id: I09a61314b1b4a5aa1e2baa52711f470802f04131
2024-02-13MLCE-1165 Model failing to load when pad is folded into Conv2dTracy Narine
* Skipping the optimization which folds pad and conv2d together for a specific case: 1x1 filter and padding size >= filter size Signed-off-by: Tracy Narine <tracy.narine@arm.com> Change-Id: I46944e9f736df1ff60469b2d2852e1bba01ab8cd
2024-02-09IVGCVSW-7569 GpuFsa Op: Add Reshape OperatorDeclan-ARM
* Add Reshape EndToEnd tests to all backends Signed-off-by: Declan-ARM <decmce01@arm.com> Change-Id: Ic6d07ba8de0cf3271ed0e4c6d604e070ccb968e3
2024-02-09IVGCVSW-8275 GpuFsa Op: Add Activation functions availableTeresa Charlin
* Currently Sigmoid and TanH Functions are implemented. Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: If9483be9201dfe47b86acc41ec7932725ac2e39e
2024-02-08IVGCVSW-7624 GpuFsa Op: Add Softmax operatorJohn Mcloughlin
* Added softmax operator support * Added test cases Signed-off-by: John Mcloughlin <john.mcloughlin@arm.com> Change-Id: I51d530b110c4cb812f5aab31ad1ee4022d81d19e
2024-02-08IVGCVSW-8276 GpuFsa Op: Add MatMulTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ib95eb0fd71106e684cb7652917b8de9f0ac73f9c
2024-02-08IVGCVSW-7570 GpuFsa Op: Add ElemenWiseBinary Operators availableTeresa Charlin
* Refactor to generalize * Add MUL Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I2ee273d50d3a8b114b5a41abc8ee7585b15e3308
2024-02-08Add and tidy up activation and elementwise binary end to end testsTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I9714c4c57e923ac775dcde2951de07cea35c40ee
2024-02-08IVGCVSW-7625 GpuFsa Op: Add Resize/Scale operatorTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I695ef452d004ed7b606020037cad681ef1fc80c3
2024-02-07IVGCVSW-7622 GpuFsa Op: Add Cast operatorTracy Narine
* Added cast operator support Signed-off-by: Tracy Narine <tracy.narine@arm.com> Change-Id: Ie12cb1559a7a059ff35e1c395bc77243499243cd
2024-02-07IVGCVSW-7623: GpuFsa Op: Add Pool2d operatorTeresa Charlin
* Add Pool2d EndToEnd tests to all backends * Add utility functions for the attributes in a separate file * Remove some unnecessary includes Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I0f82ebbf7b3301c6368462fb4fb4d4d02b246fc6
2024-02-01Removing unnecessary includes from GpuFsa operators.Colm Donelan
Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: I3d089e7f1b75596501130d3ece3a94dd326cc27e
2024-01-31IVGCVSW-7568 Implement Sub ElementwiseBinary operator GpuFsaJohn Mcloughlin
* Added support for Gpu Sub operator * Added unit tests Signed-off-by: John Mcloughlin <john.mcloughlin@arm.com> Change-Id: I1efaa485772a3716e3781566843bd50bd9bab811
2024-01-30IVGCVSW-7550 GpuFsa Op: Add ElementWiseBinary Operator ADDTracy Narine
* Adding support for Gpu Add operator * Added tests for layer support, end to end and optimization Signed-off-by: Tracy Narine <tracy.narine@arm.com> Change-Id: Ie9328d269c5c0ff60a7e10133b728ac9265033af
2024-01-26IVGCVSW-7571 GpuFsa Op: Add Depthwise Conv2dTianle Cheng
* Added DepthwiseConv2d support for GpuFsa backend. * Updated DepthwiseConv2d End-to-End test Signed-off-by: Tianle Cheng <tianle.cheng@arm.com> Change-Id: I646839980d138ae235a00990c97c6e66a4418a5e
2024-01-23IVGCVSW-7628 Update GpuFsa to use ACLs latest fixesOrlaith Monahan
* Updates to the existing GpuFsa backend to incorporate patch: https://review.mlplatform.org/c/ml/ComputeLibrary/+/10990 * Update the ACL pin to include the patch with the fixes Change-Id: I08d111265f4617657ee7f20249aeb111f64ba7a9 Signed-off-by: David Monahan <david.monahan@arm.com>
2024-01-23Minor fixes related to the LeakyRelu Activation support commit (IVGCVSW-7344)Tracy Narine
* Using the tosa defines from the serialization library to avoid compile errors in other backends * Fixing a bug in the version compat macro Signed-off-by: Tracy Narine <tracy.narine@arm.com> Change-Id: Ie4ee80666c6f8033bb72e0e6cb8ca5ef41933990
2024-01-22IVGCVSW-7165 - PreCompiledWorkload and Conv2d Integration work for GpuFsaDavid Monahan
* Add PreCompiledWorkload implementation for GpuFsa * Add ConstantWorkload implementation for GpuFsa * Add Input/Output workloads for GpuFsa * Added CopyMemGeneric workload for GpuFsa * Separate creation and validation of sketch tensors into seperate functions Signed-off-by: Kevin May <kevin.may@arm.com> Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: Ie7299a4c61073b5ca03d9f8681458869ef7ce743
2024-01-18Bugfix: Remove implicit sign conversion causing -Werror=sign-conversionFrancis Murtagh
Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: If2d5005889b8b0011e4592b46276367798556751
2024-01-17IVGCVSW-7344 Add LeakyRelu Activation support to TOSA Reference BackendTracy Narine
* Adding a one to many FP32 tosa mapping for Leaky Relu * Added a few utilities that are needed * Added new tests Signed-off-by: Tracy Narine <tracy.narine@arm.com> Change-Id: If1d7c57a523961581777a244416a7346a9310803
2024-01-03IVGCVSW-8118 Added Two-Layer and Three-Layer Maxpool2d EndToEnd tests.Tianle Cheng
Signed-off-by: Tianle Cheng <tianle.cheng@arm.com> Change-Id: I4d04fef5ce97901cd687e29adf86b18cb54a5d9a
2024-01-02Fix for Resize with align corners = true creates a memory leak when using ↵Teresa Charlin
valgrind * Add end to end unit test to CpuRef, CpuAcc and GpuAcc backends Resolves: IVGCVSW-8193 Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I7be226f084ec814ac72c2c9b3c47c07b3baf0aa5
2023-12-21Add Quantize Support to TOSA Ref BackendTeresa Charlin
* Adding a one to many tosa mapping for Quantize * Added tests * Resolves IVGCVSW-7175 Signed-off-by: John Mcloughlin <john.mcloughlin@arm.com> Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ia0852fefb618b4a29c2601b9de8b6b2731229801
2023-12-21Remove the 2 resize tests with align corners from RefEndToEnd.Teresa Charlin
* Relates to IVGCVSW-8193 and IVGCVSW-7346 Change-Id: Ieccee93672a5c73297c4ce69d1eaec588e858df0 Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I44df03acd348532a54b66541d91610d382a222b7
2023-12-20IVGCVSW-7830 Remove Reshape where possibleMike Kelly
* Remove reshape on ClBackend * Remove unnecessary restriction on NeonBackend remove Reshape Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I79940c9f8609d19b79f2fbe55225ffc8f0d90c25
2023-12-15IVGCVSW-8113 Update EndToEnd tests and TosaReference support for MaximumTianle Cheng
* Added ElementwiseBinary EndToEnd tests with inputs of the same shape to avoid Reshape * Added Slice EndToEnd tests with 4D tensors * Added TosaReference support for Maximum and TosaRefEndToEnd tests Signed-off-by: Tianle Cheng <tianle.cheng@arm.com> Change-Id: I4fa24435a75559e00b110d0e542b4f2bf07b21b4
2023-12-14Fix incorrect Split Tosa Ref outputs checkKevin May
* Resolves IVGCVSW-7918 Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: Idd15ce139f55895957378f9a9d1471e3e48989bb
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