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2021-04-28IVGCVSW-5843 Separate memory managers for WorkingMemHandlesFinn Williams
* Add inter layer memory management to WorkingMemHandle * Change Const layers to be executed once in loadedNetworkConstruction and share tensorHandle between all WorkingMemHandles * Fix various reference workloads pointing to memory in the queueDescriptor Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I69d4b3c5c84d2f5abe4540c3e624ab4f00d88226
2021-04-28IVGCVSW-5416 'Add android-nn-driver support for CASTSadik Armagan
Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I02da912e5e4ca650b367ca40fe3f5ca5baa61cbb
2021-04-14IVGCVSW-5787 Add/Update Execute() implementations in RefActivationWorkloadFinn Williams
* Added multithreaded StridedSliceEndToEndTest Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I4579db7b5959e0a22256f1bda00238c22e611dec
2021-04-12IVGCVSW-5410 Add front-end support for CASTmathad01
IVGCVSW-5415 Add TfLiteParser support for CAST * Added front end support for CAST, including support in the Reference workload, Serialization, Deserializtion, Unit tests, and TfLiteParser. Signed-off-by: mathad01 <matthew.haddon@arm.com> Change-Id: Iaf670ca5912a21ed6bc84f7f83a68b42154846bb
2021-04-09MLCE-328 Serializer/Deserializer does not support Signed64Mike Kelly
* Added support for Signed64 to flatbuffer's schema & updated source tree * Added support for Signed64 to TFLite Delegate * Added support for Signed64 to Serializer * Added support for Signed64 to Deserializer * Added unit test for ArgMinMax to Deserializer * Deprecated m_Output_Type from the ArgMinMaxDescriptor: the output type is solely determined by the DataType of the output Tensor * Fixed issue where RefArgMinMaxWorkload could output data using the wrong DataType * Added Signed64 to RefLayerSupport::IsArgMinMaxSupported as a supported type Signed-off-by: Mike Kelly <mike.kelly@arm.com> Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: Ib622c052a1f8aa3e658262f8bde5a6881a8cbe10
2021-04-07Fix graph copy memory spikeFinn Williams
* Change layer storage of ConstTensors to std::shared_ptr<ConstCpuTensorHandle> * Change clone to share ConstTensor rather than copy * Remove uses of non-const GetTensor() call * Reduce scope of non-optimized network in ExeNet, so memory can be released after use Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: Ibb2c7309d12411d21405bd6024c76bcdf5404545
2021-03-29IVGCVSW-5790 Merge async prototypeMike Kelly
* Added thread safe execution mechanism for armnn * Removed duplicate function bool Compare(T a, T b, float tolerance) * Added StridedSliceAsyncEndToEndTest * Fixed memory leak Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I2d367fc77ee7c01b8953138543e76af5e691211f
2021-03-25IVGCVSW-5736 and IVGCVSW-5743 'NonConstWeights: Update front-end and ↵Sadik Armagan
TfLiteDelegate support for FullyConnected Operator' * Added front-end support for non-const weights for FULLY_CONNECTED operator * Added FULLY_CONNECTED end-to-end test * Updated FULLY_CONNECTED operator support in TfLite Arm NN Delegate for non-const weights * Updated the version numbers Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Iffa5b9aa9297aca4c02d923cce4636c88ac21faa
2021-02-11MLCE-347 Bug fixes in Reduce: QueueDescriptor.validate and init REDUCE_MINTeresa Charlin
* Allow input tensors of any rank in ReduceQueueDescriptor::validate * Fix VTS tests failing for REDUCE_MIN due to initialization Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Id8fba1662ade4e0a967093fe5a53b275847f2393
2021-02-09MLCE-347 'REDUCE_MIN, REDUCE_MAX, REDUCE_SUM Support'Sadik Armagan
* Added TfLiteParser support for REDUCE_MIN and REDUCE_MAX operators * Added ACL workloads support for REDUCE_MIN, REDUCE_MAX, and REDUCE_SUM operators * Added TfLite Delegate support for REDUCE_MIN, REDUCE_MAX, and REDUCE_SUM operators Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I8085d59946bfd4ab78a59a61f899031ae53371a8
2021-02-03backends/reference: Add ReduceSum operation supportSadik Armagan
This patch addes ReduceSum operation support for reference backend, which computes the sum of elements across dimensions of a tensor. Changelog v1: - Fix file header descriptions. Chagelog v2: - Fix line limit issue. - Fix type conversion issue. Changelog v3: - Remove tabs. - Modify newly added file headers. Changelog v4: - Symbol on header isn't allowed so drop it from newly added file headers. Changelog v5: - Remove tabs, fix the use of brackets and align lines correctly. Changelog v6: - Add serializer and deserializer support. Changelog v7: - Fix build error add missed code. Changelog v8: - Rename ReduceSumDecriptor to ReduceDescriptor - Update m_KeepDims field data type to bool on ReduceDescriptor - Add ReduceOperation field to ReduceDescriptor - Rename ReduceSumLayer to ReduceLayer - Update ReduceLayer to use ReduceDescriptor - Update ReduceLayer::ValidateTensorShapesFromInputs() function - Rename RefReduceSumWokload to RefReduceWorkload - Update workload to use ReduceDescriptor - Update workload to use Decoders and Encoders - Remove ReduceSum.hpp and ReduceSum.cpp - Added Reduce.hpp and Reduce.cpp - Move Mean.cpp (which is implementing REDUCE_MEAN) functionality to Reduce.cpp - Update RefMeanWorkload to call Reduce function with ReduceOperation::Mean argument - Remove Mean.hpp and Mean.cpp - Update the Serializer/Deserializer ArmnnSchema.fbs for ReduceLayer, ReduceDescriptor, and ReduceOperation - Update Serializer and Deserializer for serializing/parsing ReduceLayer - Added TfLiter parser Sum test for REDUCE_SUM operator - Make corresponding changes on front-end and Ref backend to support REDUCE_SUM operator Changelog v9: - Fixed build errors. Change-Id: I8c8e034f3df73f9565b3c18eff51ecca6c542195 Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sadik Armagan <sadik.armagan@arm.com>
2020-12-17IVGCVSW-4625 Add CL Rank WorkloadDavid Monahan
* Added CL implementation of Rank Workload * Removed references to memcpy_s as it's a windows only function Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: Ia63666b9640d76a775f2ab98b3cd7e9f77b5a507
2020-11-09IVGCVSW-5091 Add Logical ops frontend and ref implJames Conroy
* Add frontend and reference implementation for logical ops NOT, AND, OR. * Unary NOT uses existing ElementwiseUnary layer and ElementwiseUnary descriptor. * Binary AND/OR uses new layer LogicalBinary and new LogicalBinary descriptor. * Add serialization/deserializion support and add missing ElementwiseUnary deserializer code. * Add additional Boolean decoder in BaseIterator.hpp. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: Id343b01174053a166de1b98b6175e04a5065f720
2020-10-23GitHub#465 Fix NonMaxSuppressionantkillerfarm
If visited flag set true, it should not be visited any more. For example, if we put 10 boxes (ordered by score) into NonMaxSuppression: * Step1: Suppose Box 2/3/6/8 are suppressed by Box 1. Box 4/5/7/9/10 survived. * Step2: Correct way: We use Box 4 to suppress the survive boxes. Prior to this commit: Box 4 may be suppressed by Box 2, even Box 2 is already suppressed by Box 1... Signed-off-by: Antkillerfarm <antkillerfarm@gmail.com> Change-Id: I38d7a84287649827a16565748592fb562b4df5d5
2020-10-13IVGCVSW-4489 Remove remaining occurrence of boost::formatMatthew Sloyan
* Replaced with fmt::format in Descriptors.cpp. * Removed remaining boost/format headers in ArmNN codebase. * Removed additional boost header in Network.cpp Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: Ib98b83bf4ec99ef98ce7a3635ec0dd478c3e43e1
2020-10-02IVGCVSW-5334 Remove remaining boost::numeric_cast from armnnMatthew Sloyan
* Floating point casts now use armnn::numeric_cast. * Also removed remaining header imports. Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: I2d37847d67f164fc0a0ae17f34d49ff3d2210c30
2020-10-01IVGCVSW-5325 Fix non-channel per axis quantizationFinn Williams
Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: Ie0cf69b2cd76d6ecedab43d3d9ae267d23bbc052
2020-09-28IVGCVSW-5325 Speed up the reference backendFinn Williams
Change-Id: Id8bd0a0418be31d975b944b54bbacb25051ffb2e Signed-off-by: Finn Williams <Finn.Williams@arm.com>
2020-09-24Add int32 and int64 ArgMax op supportInki Dae
This patch adds int32 and int64 ArgMax op support. Current ARMNN already has ArgMax op but not used, and it doesn't support int64 output type. So this patch adds a new type, Signed64, and also adds ArgMinMax computation function for int64 type support. In default, output tensor type of ArgMax op is int64 in case of tensorflow lite model so this patch makes a proper function - ArgMax op for int64 or int32 - to be called according to parsed output_type value. With this patch, ARMNN supports both types - int64 and int32 - for ArgMinMax op. Changelog v1: - Check if output data type of ArgMinMax op is valid or not. - Use template function to support int32 and int64 types of ArgMinMax function. - Keep using Signed32 as default data type of m_Output_Type. Change-Id: I7a8e7e38dd9e5acc81464571d8b4d51378fc7f14 Signed-off-by: Inki Dae <inki.dae@samsung.com>
2020-09-17IVGCVSW-5300 Remove some boost::numeric_cast from armnn/backendsMatthew Sloyan
* Replaced with armnn/utility/NumericCast.hpp * Some exclusions in reference backend * Excluded as requires float implementation in NumericCast.hpp Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: I9e4e9cd502c865452128fa04415fd6f250baa855
2020-07-06IVGCVSW-4624 Add a RANK Reference ImplementationFinn Williams
* Add Rank front end * Add Rank reference implementation * Add Rank serialization support * Add Scalar serialization support Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I06e4a468c2a84e79bae2e6c5348596bbbf853b4b
2020-07-01IVGCVSW-4903 Connect axis parameter in Gather from android to ACL.Teresa Charlin
!android-nn-driver:3302 Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ifbc49acb5272f8a36719bb68676e44817190537d
2020-06-30IVGCVSW-5007 Implement an Int32 reference Elementwise workloadFinn Williams
Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I6592169b74ac4294bc09647879aec0718c641f91
2020-06-20IVGCVSW-4707 - Add AlignCorners and HalfPixelCenters to ResizeDavid Monahan
* Added AlignCorners and HalfPixelCenters Parameters to Resize * Added Unit Tests Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: I83420a9bcb7beec9073d201448f64eb53090e1f1
2020-06-15IVGCVSW-4620 Add Fill Reference ImplementationRyan OShea
* Add Fill Reference Implementation * Refactor FP converter to use static_cast Signed-off-by: Ryan OShea <Ryan.OShea2@arm.com> Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I532e2f982981d047690755fac43a0e9cf8b17dcd
2020-06-08IVGCVSW-4860 Add tests to verify QLstm projectionJames Conroy
* Adds int16 output tensor to CpuRef impl to prevent overflow when accumulating output after projection. * Adds two remaining tests to verify QLstm on CpuRef. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: I93d7c64c4a9cc1012cb2bc052d598d4279fbd372
2020-06-05IVGCVSW-4904 Refactor CpuRef PAD WorkloadSadik Armagan
* Refactored templated workload creation * Added int8_t unit tests Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I018b7f9f20496b5f9d7445901fe0d3dd04199cd0
2020-06-03remove BOM from filesLaurent Carlier
Change-Id: Ia4b4bb3be0ed6e933c77d58f8e9879b1370e9537 Signed-off-by: Laurent Carlier <laurent.carlier@arm.com>
2020-05-30IVGCVSW-4888 Update Resize Front end for new parametersDavid Monahan
* Added AlignCorners and HalfPixelCenters to Resize and ResizeBilinear * Updated Serializer and Serializer tests !android-nn-driver:3280 Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: Ice3bb448c239b04323854641525bfe0808c03b2e
2020-05-15IVGCVSW-4831 Fix Packet header includes in backendsFinn Williams
Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: Iedfcf0ef487bd7836b1bc4ba8a0e4337dc4da391
2020-05-02IVGCVSW-4449 Add QLstm ref implementationJames Conroy
* Adds ref implemenation for new HAL 1.3 operator, QLstm. * Adds Layer and CreateWorkload unit tests. * Adds WorkloadData validate for QLstm. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: I8a721f07ff06105e6495a1a0561b9503aa8146dc
2020-04-27IVGCVSW-4668 Add TENSOR_QUANT8_ASYMM_SIGNED data type support to CpuRef ↵Sadik Armagan
operators Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I094125ba80699cc3cf5226bda6662a54e6caa988
2020-04-10IVGCVSW-4483 Remove boost::polymorphic_downcastJan Eilers
* exchange boost::polymorphic_downcast with armnn::PolymorphicDowncast * remove unnecessary includes of boost::polymorphic_downcast Signed-off-by: Jan Eilers <jan.eilers@arm.com> Change-Id: Ie603fb82860fe05fee547dc78073230cc62b2e1f
2020-04-06IVGCVSW-4485 Remove Boost assertNarumol Prangnawarat
* Change boost assert to armnn assert * Change include file to armnn assert * Fix ARMNN_ASSERT_MSG issue with multiple conditions * Change BOOST_ASSERT to BOOST_TEST where appropriate * Remove unused include statements Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I5d0fa3a37b7c1c921216de68f0073aa34702c9ff
2020-03-19IVGCVSW-4565 TENSOR_BOOL8 data type not supported in AndroidNN DriverSadik Armagan
* Enabled Boolean and Int32 data types in Reference Comparison inputs * Added decoder for Boolean data type * Refactored ClGreaterWorkload to work with any data type * Refactored NeonGreaterWorkload to work with any data type !android-nn-driver:2902 Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I92772810b744b388831c9dca0119ebf8cb7a447e
2020-03-19IVGCVSW-4516 Add ConvertFp32ToBf16Layer and Ref workload supportNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I9099a4f840fb747336f77d20a0868b64e801a310
2020-03-17IVGCVSW-4515 Add ConvertBf16ToFp32Layer and Ref workload supportNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Ida6d7e1d2c9abe0618f8b711bab9d62c011090d6
2020-03-13IVGCVSW-4512 Add BFloat16 Debug WorkloadNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Id179cb4774a4565e5e905e5fe4c34299178644de
2020-03-13IVGCVSW-4511 Add BFloat16 to RefLayerSupport and unit testsNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Ifaae4d5aac468ba927b2c6a4bf31b8c8522aeb2e
2020-03-10IVGCVSW-4482 Remove boost::ignore_unusedJan Eilers
!referencetests:229377 Signed-off-by: Jan Eilers <jan.eilers@arm.com> Change-Id: Ia9b360b4a057fe7bbce5b268092627c09a0dba82
2020-03-09IVGCVSW-4517 Implement BFloat16 Encoder and DecoderNarumol Prangnawarat
* Add ConvertFloat32ToBFloat16 * Add ConvertBFloat16ToFloat32 * Add BFloat16Encoder * Add BFloat16Decoder * Unit tests Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I198888384c923aba28cfbed09a02edc6f8194b3e
2020-03-02IVGCVSW-4440 : Add HARD_SWISH Support to Activation in CpuRefColm Donelan
* Add a new Activiation type of HardSwish. * Add CpuRef support and tests. Signed-off-by: Colm Donelan <Colm.Donelan@arm.com> Change-Id: I68c3840aa45b7a27d5e416a5d50fe8f99f003ce8
2020-03-02IVGCVSW-4375 Add support for TransposeMike Kelly
* Added TransposeLayer * Added CL, Neon and Ref Workloads * Added Transpose utilities * Added Serializer and Deserializer support * Added Quantizer support Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I04c755ba7cb5b1edf72b3c9f3c0314878032e3c7
2020-02-28IVGCVSW-4439: Adding Elu support to ActivationDavid Monahan
* Added CpuRef implementation * Added Unit Tests * Added Quantizer Test * Enabled Tests for Neon and CL backends on fp32 only * Added to Serializer Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: Ic23e1797dbc9352b40678c389d7fe2b836b582ea
2020-02-19IVGCVSW-4472 Yolo v3 ExecuteNetwork failingKeith Davis
* Add Debug workload for QAsymmS8/U8 * Change Dequantize tests to test AsymmS8 instead of SymmS8 * Fix incorrect supportedness within RefLayerSupport Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: Ie51f1e33c564d46c86bf0150b1addda3fc093d13
2020-02-17IVGCVSW-4436 Add ExecuteNetwork test for mobilenet_v2_int8Keith Davis
* Add QAsymmS8 to QueueDescriptor supportedTypes * Add QSymmS8/QAsymmS8 to RefLayerSupport supportedTypes * Some additional comments and refactoring Change-Id: I8567314452e6e8f6f69cb6e458ee147d3fc92fab Signed-off-by: Keith Davis <keith.davis@arm.com>
2020-02-07IVGCVSW-4386 Add ArmNN reference support for QAsymmS8Ryan OShea
* Added Quantization Scheme for QAsymmS8 * Added Unit Tests for QAsymmS8 * Renamed QAsymm8 calls to QAsymmU8 Signed-off-by: Ryan OShea <Ryan.OShea2@arm.com> Change-Id: I897b4e018ba1d808cc3f8c113f2be2dbad49c8db
2020-02-07MLCE-139: add capability to align corners for bilinear resizeSang-Hoon Park
* Add parsing of the related parameter to TfLiteParser * Update ResizeDescriptor to store the additional parameter * Update NEON/CL workload to pass the additional parameter. * Update Reference workload to pass and handle the additional parameter. !ComputeLibrary:2538 !ComputeLibrary:2569 !armnn:2612 Signed-off-by: Sang-Hoon Park <sang-hoon.park@arm.com> Change-Id: Id149e1c24c2abed7e9dd81939acf54dfabfcdfd2
2020-01-31IVGCVSW-4390 Refactor QUANTIZE to make use of Decoder/Encoder typesKeith Davis
* Add no-ops for CL/NEON Uint8 * Refactor Quantize workload to Decoder/Encoder types Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I80b09de528299b925e2ac38acd9a5019b8d3e4ac
2020-01-28IVGCVSW-4306 Verify the tflite Yolo v3Keith Davis
* Added debug layer support for QSymmS8 * QSymmS8 support for workloads Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I51af92fadc0be290629dd9198beab5abef9e351f
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