aboutsummaryrefslogtreecommitdiff
path: root/src/backends/reference/test/RefLayerTests.cpp
AgeCommit message (Collapse)Author
2020-06-24IVGCVSW-4621 Add CL FILL WorkloadSadik Armagan
* Add CL workload for Fill Operator * Enabled Fill operator tests on CL * CLFill function does not have validate() function yet IsLayerSupported() function return true at the moment * Enabled int32 to tests on backends Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I9f8cc6d1c86f832ba46a8d170572f4cfcde9ab17
2020-06-20IVGCVSW-4707 - Add AlignCorners and HalfPixelCenters to ResizeDavid Monahan
* Added AlignCorners and HalfPixelCenters Parameters to Resize * Added Unit Tests Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: I83420a9bcb7beec9073d201448f64eb53090e1f1
2020-06-15IVGCVSW-4620 Add Fill Reference ImplementationRyan OShea
* Add Fill Reference Implementation * Refactor FP converter to use static_cast Signed-off-by: Ryan OShea <Ryan.OShea2@arm.com> Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I532e2f982981d047690755fac43a0e9cf8b17dcd
2020-06-08IVGCVSW-4860 Add tests to verify QLstm projectionJames Conroy
* Adds int16 output tensor to CpuRef impl to prevent overflow when accumulating output after projection. * Adds two remaining tests to verify QLstm on CpuRef. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: I93d7c64c4a9cc1012cb2bc052d598d4279fbd372
2020-06-05IVGCVSW-4904 Refactor CpuRef PAD WorkloadSadik Armagan
* Refactored templated workload creation * Added int8_t unit tests Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I018b7f9f20496b5f9d7445901fe0d3dd04199cd0
2020-06-03remove BOM from filesLaurent Carlier
Change-Id: Ia4b4bb3be0ed6e933c77d58f8e9879b1370e9537 Signed-off-by: Laurent Carlier <laurent.carlier@arm.com>
2020-05-29IVGCVSW-3847 Support INT32 in Gather operatorTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ica217d3e4fbcdef1315554ea5d5c4720124696c3
2020-05-27IVGCVSW-4200 Add CL EXP WorkloadSadik Armagan
IVGCVSW-4203 Add Neon EXP Workload * Added CL EXP operator workload * Added EXP test suite * Enabled EXP tests on ACL and Ref Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I793d31af1b2e3fe86b0bec6d9e5de503c5dab970
2020-05-25IVGCVSW-4863 ADD,SUB,DIV,MUL,MAXIMUM and MINIMUM int32 VTS testTeresa Charlin
skipped in CpuRef Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I1c870ac258e8c3805a95b259cb40731f8e81541e
2020-05-25IVGCVSW-4604 ARGMINMAX float16 VTS test skipped in CpuRefTeresa Charlin
Change-Id: I75cca9804a67f629cddc83671397a84640e9bf0e Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
2020-05-02IVGCVSW-4449 Add QLstm ref implementationJames Conroy
* Adds ref implemenation for new HAL 1.3 operator, QLstm. * Adds Layer and CreateWorkload unit tests. * Adds WorkloadData validate for QLstm. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: I8a721f07ff06105e6495a1a0561b9503aa8146dc
2020-04-27IVGCVSW-4668 Add TENSOR_QUANT8_ASYMM_SIGNED data type support to CpuRef ↵Sadik Armagan
operators Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I094125ba80699cc3cf5226bda6662a54e6caa988
2020-04-24IVGCVSW-4686 Fix NNT GeneratedTests Abs_int32Kevin May
* Add Signed32 to WorkloadData for AbsQueueDescriptor * Add missing supported tests to Ref and Neon Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: Iba9d29fedeb1d2e985272c9299ea42ba2571687b
2020-04-01IVGCVSW-4643 Add Convolution2D tests with Bfloat16 input and Float32 outputNarumol Prangnawarat
* Modify SimpleConvolution2dNhwcTestImpl to allow different input and out types * Add unit tests for Conv2D with Bfloat16 input and Float32 output to compare the accuracy with Float32 for small value inputs and big value inputs Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Ia59c92a22001b41f2681dafb951203a2223d3367
2020-03-30IVGCVSW-4603 Support comparison operators in CLTeresa Charlin
* Deprecate ClGreaterWorkload * Add ClComparisonWorkload to encompass all comparison operators Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ida0ed7f59899d75b0fe7de1e7433b1ade018c6f1
2020-03-24IVGCVSW-3813 Add Unary Elementwise Operation 'NEG' support to the ↵Sadik Armagan
android-nn-driver * Implemented ClNegWorkload * Implemented NeonNegWorkload * Enabled 'NEG' operator on CL and Neon as well as Ref * Implemented unit tests for 'NEG' operator Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I3d7a892692716636cae6bdf8ddd238e3d1ea064f
2020-03-19IVGCVSW-4516 Add ConvertFp32ToBf16Layer and Ref workload supportNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I9099a4f840fb747336f77d20a0868b64e801a310
2020-03-17IVGCVSW-4515 Add ConvertBf16ToFp32Layer and Ref workload supportNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Ida6d7e1d2c9abe0618f8b711bab9d62c011090d6
2020-03-13IVGCVSW-4512 Add BFloat16 Debug WorkloadNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Id179cb4774a4565e5e905e5fe4c34299178644de
2020-03-13IVGCVSW-4511 Add BFloat16 to RefLayerSupport and unit testsNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Ifaae4d5aac468ba927b2c6a4bf31b8c8522aeb2e
2020-03-02IVGCVSW-4440 : Add HARD_SWISH Support to Activation in CpuRefColm Donelan
* Add a new Activiation type of HardSwish. * Add CpuRef support and tests. Signed-off-by: Colm Donelan <Colm.Donelan@arm.com> Change-Id: I68c3840aa45b7a27d5e416a5d50fe8f99f003ce8
2020-03-02IVGCVSW-4375 Add support for TransposeMike Kelly
* Added TransposeLayer * Added CL, Neon and Ref Workloads * Added Transpose utilities * Added Serializer and Deserializer support * Added Quantizer support Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I04c755ba7cb5b1edf72b3c9f3c0314878032e3c7
2020-02-28IVGCVSW-4439: Adding Elu support to ActivationDavid Monahan
* Added CpuRef implementation * Added Unit Tests * Added Quantizer Test * Enabled Tests for Neon and CL backends on fp32 only * Added to Serializer Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: Ic23e1797dbc9352b40678c389d7fe2b836b582ea
2020-02-07IVGCVSW-4386 Add ArmNN reference support for QAsymmS8Ryan OShea
* Added Quantization Scheme for QAsymmS8 * Added Unit Tests for QAsymmS8 * Renamed QAsymm8 calls to QAsymmU8 Signed-off-by: Ryan OShea <Ryan.OShea2@arm.com> Change-Id: I897b4e018ba1d808cc3f8c113f2be2dbad49c8db
2020-01-13Rename quantized data types to remove ambiguity for signed/unsigned payloadsDerek Lamberti
!android-nn-driver:2572 Change-Id: I8fe52ceb09987b3d05c539409510f535165455cc Signed-off-by: Derek Lamberti <derek.lamberti@arm.com>
2019-12-09IVGCVSW-4211 Add Signed 8 bit Quantisation support into the Reference backendFinn Williams
!android-nn-driver:2435 Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I10ecd4a8937725953396805f33a3562a5384c4d4
2019-11-13IVGCVSW-4128 Add Signed32 to supported input types for Ref ArgMinMaxFrancis Murtagh
* Enabled RefLayerTests for Signed32 Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: Idbe6fb7607c7e44a8df560b55f28c64a4c4286cd
2019-11-12IVGCVSW-4079 Add support of per-axis quantization to DepthwiseConvolution2dTeresa Charlin
!android-nn-driver:2260 Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Iad93c1940568ffa65ed314c8871ea66caf4f9e4a
2019-11-12IVGCVSW-3839 Add support of per-axis quantization to reference ↵Aron Virginas-Tar
TransposeConvolution2d Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: Ie0dc1204eee925adfb1e59aba3f1137178302184
2019-11-06IVGCVSW-3837 Add support for per-axis quantization to reference ↵Aron Virginas-Tar
Convolution2d workload Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: I0ac08ba4864d48e6f64c4ac645dad8ea850be112
2019-11-06IVGCVSW-4038 Convert Strided_Slice Shrink_Axis_Mask Parameter to ACL formatFrancis Murtagh
* Add conversion method to reverse bits in Shrink_Axis_Mask * Add Unit tests for Neon, CL and Reference backends * Fix supportedness of constant layer which is causing error in DeepSpeech Uint8 * Also convert the Begin_Mask and End_Mask Change-Id: I448b083c3463558e8fb5204923ab554cd43264ba Signed-off-by: Francis Murtagh <francis.murtagh@arm.com>
2019-11-04Add fp16 support for dequantizeJan Eilers
* Changed RefDequantizeWorkload to use Encoder/Decoder * Added related unit tests for Cl, Neon and Ref Signed-off-by: Jan Eilers <jan.eilers@arm.com> Change-Id: Ic2fd4103090dd2127c6859b49305736f7b2dfb05
2019-10-21IVGCVSW-3999 Add unit tests for new comparison operationsAron Virginas-Tar
* Refactored existing tests for Equal and Greater and moved them to ComparisonTestImpl.cpp * Removed EqualTestImpl.cpp and GreaterTestImpl.cpp * Added new unit tests for GreaterOrEqual, Less, LessOrEqual and NotEqual Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: I25013200beb1acb88e83b813c5382cb277c74cd7
2019-10-15IVGCVSW-3975 Add reference workload for LOG_SOFTMAXAron Virginas-Tar
Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: I10bb7133e0e2d6d7199abdf39562b1226bbbd3e7
2019-10-09IVGCVSW-3888 Add INSTANCE_NORMALIZATION Reference implementationKevin May
Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: I725022f86e990c482ea323fc90fd136fe493ed68
2019-10-03IVGCVSW-3696 Add NEON ArgMinMax workload and testsJames Conroy
* Added layer tests and fixed WorkloadData validate. * Also enabled copy to/from NEON for Signed32. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: I5e961f88434e18d5a8ebff956d20a1c2cf1b50bb
2019-09-24IVGCVSW-3885 Add reference workload for DepthToSpaceAron Virginas-Tar
Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: Id937dc4425884ad1985dcdfaae8bf3fb64f0c766
2019-09-19IVGCVSW-3723 Adding reference workload support for ArgMinMaxNikhil Raj
Change-Id: I65209ecec4e3abf808163239748d6e830568c2e3 Signed-off-by: Nikhil Raj <nikhil.raj@arm.com>
2019-09-18IVGCVSW-3878 Add reference workload for SLICEAron Virginas-Tar
* Added reference workload implementation and layer tests for all supported tensor dimensions (1d, 2d, 3d, 4d) Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: I40eb300828933e9183027281105d1a7e597d1569
2019-09-16IVGCVSW-3660 Add SQRT unit tests for Neon and CL backendsSadik Armagan
Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Iaaff33f578c4d88f6c03c8de4af71d5347178eaa
2019-09-12IVGCVSW-3857 Add Reference FP16 workload support to remaining layersMatthew Jackson
* Adds Reference FP16 support and unit tests for layers not already supported !referencetests:202156 Signed-off-by: Matthew Jackson <matthew.jackson@arm.com> Change-Id: I6fc9b9ce2809e163f72e27e877025c8fb85d9fbe
2019-09-10IVGCVSW-3824 Implement Float 16 Encoder and DecoderMatthew Jackson
* Implement Float 16 Encoder and Decoder * Add Stack Float 16 layer and create workload tests Signed-off-by: Matthew Jackson <matthew.jackson@arm.com> Change-Id: Ice4678226f4d22c06ebcc6db3052d42ce0c1bd67
2019-09-06IVGCVSW-3740 Add Reference Workload support for ABSSadik Armagan
* Implemented RefAbsWorkload and unit tests Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Ibfcdb2b37fd8d240c181f96856e2c997a4b88914
2019-08-30IVGCVSW-3381 Break up LayerTests.hpp into more manageable filesAron Virginas-Tar
Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: Icf39434f09fd340ad664cb3b97b8bee6d9da4838
2019-08-26IVGCVSW-3575 Fix DepthwiseConvolution VTS Test FailuresKevin May
Failing VTS tests were "NeuralnetworksHidlTest.depthwise_conv2d_*" In depthwise convolution there was a difference in weight tensor channel order between the reference and ACL implementations. This specifically related to NCHW. This commit: * Adds ReorderWeightChannelsForAcl to WorkloadUtils which will correct the weight tensor channel order. * Add unit tests to detect this problem. Signed-off-by: Colm Donelan <Colm.Donelan@arm.com> Change-Id: Icaeac08e14b3d5da9e222ad2f118db55ebb15d09
2019-08-16IVGCVSW-3639 Add 5d tensor supportMatthew Jackson
* Increased MaxNumOfTensorDimensions and fixed issues related to its use * Fixed issues caused by assuming 5d tensors are invalid * Updated ArmComputeTensorUtils for 5d tensors * Added 5d tensor unit tests for add, mul, stack and reshape (needed by IVGCVSW-3527) Signed-off-by: Matthew Jackson <matthew.jackson@arm.com> Change-Id: I5bcd64942d0d04efcc6c5acb240ad4b88e010743
2019-08-13IVGCVSW-3616 Add multi-channel unit test for TransposeConvolution2dAron Virginas-Tar
Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: Ib9271920b39fb9d730006c79a322e32008096b56
2019-07-26IVGCVSW-3537 Add support for L2 Normalization with < 4 dimensional tensorsMatthew Jackson
* Fix reference L2 Normalization workload to support < 4 dimensional tensors * Add unit test for L2 Normalization with 2d tensor to Reference, Neon and CL test suites * Fix typo in StackLayer Signed-off-by: Matthew Jackson <matthew.jackson@arm.com> Change-Id: I48a6a1289bcb02955b24f261bc70b467bd1abc23
2019-07-23IVGCVSW-3536 Add Axis parameter to reference Softmax implementationFrancis Murtagh
* Add Axis parameter to Softmax Descriptor * Add new reference implementation for Softmax using Axis parameter * Add unit tests to cover each Axis Change-Id: Iafac2275d2212337456f2b1b56b0f76f77fb9543 Signed-off-by: Francis Murtagh <francis.murtagh@arm.com>
2019-07-22IVGCVSW-3368 Add reference support for depthwise multiplier > 3Matthew Jackson
* Remove multiplier check in TfLite parser * Add reference unit test for depthwise multipler of 64, as in DeepSpeaker Signed-off-by: Matthew Jackson <matthew.jackson@arm.com> Change-Id: I787339ab4c4d269333985353d191202d070906ba
generated by cgit v1.2.1 (git 2.23.0) at 2024-07-09 12:48:42 +0000