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2023-07-27IVGCVSW-2292 Tile Operator Neon ImplementationDavid Monahan
* Added Implementation of the Tile Operator Workload to Neon * Added calls to the existing unittests * Added Documentation Signed-off-by: David Monahan <david.monahan@arm.com> Change-Id: I0030ffe514215c79f5629d20671254dde9bec452
2023-07-21IVGCVSW-7830 Clean upMike Kelly
* Follow up review to clean up whitespace and copyright errors mentioned in https://review.mlplatform.org/c/ml/armnn/+/9885 * Added BinaryElementwiseOperation to .dot files * Refactored ConnectedToSplitterWithMoreThan4Dims function to more generally useful ConnectedToLayerType function Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I0e3d0895888f3a3f0a9758ce30bc031aba50812b
2023-07-20IVGCVSW-7850 block non const bias on NEON Depthwise conv.Colm Donelan
* There's currently a problem with using a non const bias value in NeonDepthwiseConvolution. We will block it for the moment. Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: Ifd206cfd25a2305a80f8b0a88e07747e79468d18
2023-07-20IVGCVSW-7849 and IVGCVSW-7825 block non const bias on NEON CONV2D.Colm Donelan
* There's currently a problem with using a non const bias value in NeonConvolution2d. We will block it for the moment. Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: Ia020cf48f7d5e0642f7763e82501f06ad89945d8
2023-07-10IVGCVSW-7785 3D tensors in BATCH_TO_SPACE and SPACE_TO_BATCH in CpuAcc & GpuAccTeresa Charlin
* Add Reshape layers before and after to extend support for 3D tensors, as ACL only supports 4D tensors for those layers * Add Unit Tests Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I4431185ce3a3b2f595d2a79bdda7095212d1c52d
2023-06-26Update ACL pin to c952596e70f2fe0073029f053e329a4e930ced8cNikhil Raj
* activationInfo passed in directly to configure() rather than part of matMulInfo Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I546def1c1e1cabaf50629f7d78ae0ba459766ed4
2023-06-19Update ACL pin to 043613fbb199e2c4fdd12c2c9a1785db9b0c45faNikhil Raj
* Break up Utils.h a bit to reduce unused code being included everywhere * Add FullyConnectedLayerInfo.h to ArmComputeUtils.hpp and remove Types.h * Add MatMulInfo.h to Neon and CL BatchMatMulWokloads Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: I2fbe90cb40dc59add90735dafe9fef9aab3fbf06
2023-06-14IVGCVSW-7791 Enable dynamic bias in Conv in CpuAcc and GpuAccKevin May
Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: I722a9e4f3dba2500c624c6326f74085277e0d631
2023-06-07IVGCVSW-7789 Enable dynamic bias in Depthwise Convolution in CpuAccTeresa Charlin
* Dynamic bias are supported by CpuAcc for this layer * Indentation and const modifiers minor changes Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: I3b25f14feea55f746c254a832d97e21a1551ca36
2023-06-07Fix incorrect validation of Unidirectional Sequence LSTM on Cl and NeonNarumol Prangnawarat
Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I54c60fb98b9c560c300572f46d42b13aec7e402e
2023-05-23MLCE-1022 Fix failure on UnidirectionalSequenceLstm OperatorNarumol Prangnawarat
* Fix failure to parse UnidirectionalSequenceLstm Operator on CpuAcc * Fix failure to parse UnidirectionalSequenceLstm Operator on GpuAcc * Fix IsLayerSupported tests when there are multiple otutputs Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Ia690f34d3c7fae87bd36c97056a3ff71baa865f6
2023-05-23IVGCVSW-7732 Enable dynamic bias in FullyConnected in CpuAcc and GpuAccTeresa Charlin
* Dynamic bias are supported by ACL for this layer. Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I428bd42a97e0c26c72f9925e3cb209c2fc9a650d
2023-05-18IVGCVSW-7400 POW IVGCVSW-7278 SQUARED_DIFFERENCE to CpuAcc and GpuAccJohn Mcloughlin
* Add POW SQUARED_DIFFERENCE and Unit tests for CpuAcc and GpuAcc Signed-off-by: John Mcloughlin <john.mcloughlin@arm.com> Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ifa78af2a2fda2074586d8e4d9a506b1b13fa5755
2023-05-11Revert "IVGCVSW-7454 Enable dynamic bias in CpuAcc and GpuAcc in Conv2d ↵TeresaARM
DWConv and FC" This reverts commit fecd9ed396705a17805ffc49839bd82ae24c892b. Reason for revert: IVGCVSW-7727 Dynamic bias CTS failing Change-Id: I53f67d60fca0e60a81298f90450ceef26b97c321 Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
2023-05-09IVGCVSW-7454 Enable dynamic bias in CpuAcc and GpuAcc in Conv2d DWConv and FCTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ib6914a9a208475b68e969eba6f70fae4061efa9b
2023-05-08IVGCVSW-7454 Fix CpuAcc FC dynamic weightsTeresa Charlin
* Pass to ACL the flag for constant weights and bias in FC, conv and DWconv workloads Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Iae2810c8d1a402d4afc1e757846665315a80d3ea
2023-05-08IVGCVSW-7307 Add CpuAcc Batch MatMul WorkloadTeresa Charlin
* Call dedicated MatMul kernel in ACL * Add int8 tests * Add int8 to documentation * Force tensors to be dynamic (nonConst) as per request of ACL Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I992ae9aae1174214607bf29305f21cdeaf3fdc1b
2023-04-28Make Convert workloads use arm_compute::NECast in CpuAcc backendMatthew Bentham
NECast can use conversion instructions where they are available so this should in general be faster. Signed-off-by: Matthew Bentham <Matthew.Bentham@arm.com> Change-Id: I3f259e17b280a4f4c36f363965ffbc8ee8c4c29f
2023-04-11IVGCVSW-7507 Pass m_Crops in BatchToSpaceND CpuAcc and GpuAcc workloadsTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I902c9187eefe7595271312fdc16273f7aa3d41cd
2022-12-12IVGCVSW-7209 Remove deprecated code due to be removed in 23.02Mike Kelly
* Removed weights and bias from Convolution, DepthwiseConv & FullyConnected layers * Removed the weight and bias ConstTensorHandles from the QueueDescriptors * Updated Workloads to take tensors from WorkloadInfo rather than the QueueDescriptors * Removed unused RedirectMembersToConstantInputs optimization and tests. Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I9ffcdc4a1c0dff725539dd69fc435b700bd98a56
2022-11-16IVGCVSW-7214 Disable BF16-Turbo-Mode and remove conversion layersRyan OShea
- Remove Bf16ToFp32 Conversion Layer - Remove Fp32ToBf16 Conversion Layer - Remove B16 Conversion tests * Throw exception if m_ReduceFp32ToBf16 optimzer option is set to true * Provide comments to enable fast math in order to use bf16 * Update docs to inform users to enable fast math for bf16 Execute Network Changes * Require bf16_turbo_mode to also have fast_math_enabled set to true - Remove setting m_ReduceFp32ToBf16 optimizer option Signed-off-by: Ryan OShea <ryan.oshea3@arm.com> Change-Id: Ibaa6da9d29c96a1ce32ff5196b0847fde9f04a1c
2022-10-28IVGCVSW-6494 Add CpuAcc Batch MatMul Workload Fp32Teresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I2def6995f81d33e68f1ea45d8d19a1e6294049b1
2022-08-05IVGCVSW-6889 Seg fault running ExeNet with --bf16-turbo-mode on fpgaFrancis Murtagh
* Added case for Bf16 to switch and changed Assertion to Exception so it shows up in Release build. Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I817260dc7b7667386c4aa734bea649383866a785
2022-05-23MLCE-825: Give reason when workload unsupported for Non Constant Weights/BiasFrancis Murtagh
* BackendHelper.cpp IsXXXLayerSupported doesn't get as far as Neon/Cl Validate functions where arm_compute::Status is returned. * Conv2d, Depthwise, DilatedDepthwise and FullyConnected * Tidy up if() -> if () * Clean up logic in FullyConnected so that isLayerSupported gets called Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I5da1a882f4a2f55e90aa984b2b9548a847cb3a2d
2022-05-17IVGCVSW-6126 ConstTensorsAsInput: Conv2d - BackendsCathal Corbett
!android-nn-driver:7477 Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: Ibf633ccccc385bd980934ff829407d21981323ef
2022-05-16IVGCVSW-6124 ConstTensorsAsInput: Conv2d - FrontEndKeith Davis
* Update Front-end and Tools. * Updated Serializer, Deserializer and unit tests to reflect this. * Updated TfLiteDelegate, TfLiteParser and OnnxParser. * Updated Ref. * Fixed resulting Neon / CL tests * Unified optimizers for conv2d ops * Optimizer Fix - Fp32ToBf16 * Partial implementation for ACL backends to fix VTS failures !android-nn-driver:7477 Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I5fb18877f7ee32643e15a9818945356274bb401b
2022-05-13IVGCVSW-6175 Add Pooling3d to NeonRyan OShea
* Add IsSupported for Pooling3d * Add CreateWorkload case for Pooling3d * Create new NeonPooling3dWorkload header and source files * Add Pooling3d workload to NeonWorkloads.hpp * Add float32 tests for Pooling3d workload * Add Uint8 tests for Cl and NE pooling3d Signed-off-by: Ryan OShea <ryan.oshea3@arm.com> Change-Id: Ic992e1233d1eb8db52df2c8446183df1c907bc4d
2022-05-13IVGCVSW-6260 ConstTensorsAsInput: Fully Connected Cl and Neon support.Cathal Corbett
* IVGCVSW-6940 ConstTensorsAsInput: DepthwiseConvolution2d - Complete Neon and Cl Bug Fix * Bug fix to enable Cl and Neon Backend Compatibility ConstantTensorsAsInputs * Updated Cl and Neon FullyConnected workloads to handle constant weights and bias as inputs rather than reading from member variables. * Prevent non const weights and biases passing CL and NEON validate for Depthwise Convolution. Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: I0f505ff5998a183152f843d0f6cc74327ba920e7
2022-05-12IVGCVSW-6940 ConstTensorsAsInput: DepthwiseConvolution2d - Complete ACLCathal Corbett
* Added backend specific optimization & test for CpuAcc and GpuAcc: PermuteDepthwiseConv2dWeights Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: I600476b2e9c557a39818a574c1091c9d650b21b1
2022-05-10IVGCVSW-6936 Sqrt for CpuRef, CpuAcc and GpuAccTeresa Charlin
* Add Unit Tests * Bug Fix: add Sqrt to Neon and Cl workload factories Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I0db1d813a4e7d15431e87e825e6d14e61f5ffb7d
2022-05-09IVGCVSW-6862 Use same datatype for all containers of indices in NeonGatherNdTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I6b1c7c1c499dc93aa58fa9f58b64fb664e8bcc56
2022-05-06IVGCVSW-6862 Modify GATHERNd Neon workloadTeresa Charlin
* Add validate for all layers for GatherNd * Fix convert policy for Mul Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I0f2bae5107607ba3c02b5546f60dd9623cd95853
2022-05-06IVGCVSW-6936 Add SQRT support to NeonTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I195957541069cb52cdd2c8aead0e4a34498a6f38
2022-05-05IVGCVSW-6862 Add GATHERNd Neon workloadTeresa Charlin
* Changing the test in the delegate to match one of the unit tests Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I553ca266116ba8ee173fc951ab1ffd2b6eed1428
2022-05-05IVGCVSW-6806 Add Unidirectional Sequence Lstm support to NeonMike Kelly
* Corrected TensorInfo order for IsUnidirectionalSequenceLstmSupported * outputStateOut TensorInfo is not optional. * cellStateOut TensorInfo is not optional. * TensorInfo Order matches other QLSTM/LSTM layers. * Added missing parameters to UnidirectionalSequenceLstmOperator for delegate. * Added quantized UnidirectionalSequenceLstm support to Neon !android-nn-driver:7457 Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I26dde1bb96793dd25eb9081ca5ae5f63752288c4
2022-03-23IVGCVSW-6706 Move headers to profiling/client/includeJim Flynn
!android-nn-driver:7337 Change-Id: Ide401623829cc99fb9b51e9bbce3482ce706a8dd Signed-off-by: Jim Flynn <jim.flynn@arm.com>
2022-03-03Revert "Revert "IVGCVSW-6267 Add support of Unidirectional Sequence Lstm ↵Cathal Corbett
fp32/fp16 to Cl"" This reverts commit 79cef69b1ec58f9ce010461eaaad04c896a4fe15. Reason for revert: 22.05 release. Change-Id: Id2ecbf563e8808694fb8605604e8c3c39c29cec2
2022-03-03Revert "Revert "IVGCVSW-6268 Add support of Unidirectional Sequence Lstm ↵Cathal Corbett
fp32/fp16 to Neon"" This reverts commit f87b90e4dbb906436cf205a2a19e199bfe9224ed. Reason for revert: 22.02 release. Change-Id: I1ca5a79a8957908f655a6c4e79eefa24c5aec645
2022-02-23Revert "IVGCVSW-6268 Add support of Unidirectional Sequence Lstm fp32/fp16 ↵Cathal Corbett
to Neon" This reverts commit b0baff73b1574a198e57d46fcd704cedc43cea16. Reason for revert: cannot update ACL pin until 22.02 release. Change-Id: I049a125ba3b6a9b1cd6514ef9dd14d807773ed00
2022-02-23Revert "IVGCVSW-6267 Add support of Unidirectional Sequence Lstm fp32/fp16 ↵Cathal Corbett
to Cl" This reverts commit ad9171701e6032b3ddf3573f85780bae30c512c6. Reason for revert: cannot update ACL pin until 22.02 release. !ComputeLibrary:7150 Change-Id: Ic19a3c2fe5d6f7e5568174f18ea73684b269f72d
2022-02-22IVGCVSW-6267 Add support of Unidirectional Sequence Lstm fp32/fp16 to ClCathal Corbett
!ComputeLibrary:7150 Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: I01690e6555978d93c41d09bbe5378683bc925f61
2022-02-21IVGCVSW-6268 Add support of Unidirectional Sequence Lstm fp32/fp16 to NeonCathal Corbett
!ComputeLibrary:7150 Signed-off-by: Cathal Corbett <cathal.corbett@arm.com> Change-Id: I3de48ffc8d08c95a22705e2b68d069791bddae73
2022-02-10IVGCVSW-6700 Add override functions to all typed Neon/CL workloadsDavid Monahan
* Neon and CL workloads which inherit from TypedWorkload instead of the BaseWorklod for their backend do not contain the correct ReplaceInputTensorHandle/ReplaceOutputTensorHandle and Reconfigure functions. So they have been added directly. * Removed the Profiling call from ClConvolution2dWorkload::Reconfigure() to avoid a segfault Signed-off-by: David Monahan <David.Monahan@arm.com> Change-Id: I7b9d1b48fdb17db1662dc03c22acc746340ce73f
2022-02-08Handle optional biases better in Neon/Cl FullyConnected workloadsMatthew Bentham
Use armnn::Optional for optional bias TensorInfos, similar to how it's already done in Convolution etc. Fixes some test failures found using -fsanitize=undefined Change-Id: I7b887e63e2ffab14aeab14415069be738d938ebb Signed-off-by: Matthew Bentham <matthew.bentham@arm.com>
2022-01-31IVGCVSW-6552 Add support of aligned host memoryNarumol Prangnawarat
* Add AllocatedData functions to OutputHandler * Enable import aligned memory in ImportInputs * Enable import aligned memory in ImportOutputs * Allow to import input and output if the memory is aligned * Implement Reconfigure function on ClConvolution2dWorkload * End-to-end test on Ref and Cl to ensure that input and output memory are imported when aligned Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I9e5e4c26d1ac2f1d806803ade5f64c6479c51718
2022-01-26IVGCVSW-6685-6686 Modify workloads to extend Neon/Cl BaseWorkloadTeresa Charlin
* Neon workloads to extend NeonBaseWorkload instead of BaseWorkload * Cl workload to extend ClBaseWorkload instead of BaseWorkload Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I8f39a31a89a8865ac4acf18573ab290d548d2864
2022-01-26IVGCVSW-6683-6684 Add ClBaseWorkload and NeonBaseWorkloadTeresa Charlin
* Neon/Cl Activation workloads inherit from Cl/Neon BaseWorkload * Unit Test for ReplaceTensorHandle functions Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I985e34b93a96405735402a6d3b947957afbe2857
2021-12-15IVGCVSW-6626 Promote backend headers in backendCommon to armnn/backendsColm Donelan
Move the following header files from backendsCommon to armnn/backends. * MemCopyWorkload.hpp * TensorHandle.hpp * Workload.hpp * WorkloadData.hpp * WorkloadFactory.hpp Replace them with forwarding headers and a pragma deprecation message. Resolve the deprecation messages in Arm NN code. Signed-off-by: Colm Donelan <colm.donelan@arm.com> Change-Id: I47f116b30f86e478c9057795bc518c391a8ae514
2021-11-18IVGCVSW-6520 Extend pad workload for CpuAcc to support mirror paddingTeresa Charlin
* Add UnitTest for CpuAcc !ComputeLibrary: 6641 Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ic96b9e28d133cef73312b4ac793325f5e69b3d4d
2021-11-03Bug Fix in CpuAcc and GpuAcc workload: Gather has 2 inputsTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ifbb9332c78c843c5b937c4e1b50a8f5a75409e73
generated by cgit v1.2.1 (git 2.23.0) at 2024-07-25 19:47:57 +0000