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2021-04-20IVGCVSW-5816 Constant memory accessFrancis Murtagh
* Add new class ManagedConstTensorHandle to Unmap when out of scope * Integrate into existing layers that have constants * Add unit tests Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I0a05e14e438804b37e9862e76b5ca329483f6b45
2021-04-12IVGCVSW-5410 Add front-end support for CASTmathad01
IVGCVSW-5415 Add TfLiteParser support for CAST * Added front end support for CAST, including support in the Reference workload, Serialization, Deserializtion, Unit tests, and TfLiteParser. Signed-off-by: mathad01 <matthew.haddon@arm.com> Change-Id: Iaf670ca5912a21ed6bc84f7f83a68b42154846bb
2021-04-09MLCE-328 Serializer/Deserializer does not support Signed64Mike Kelly
* Added support for Signed64 to flatbuffer's schema & updated source tree * Added support for Signed64 to TFLite Delegate * Added support for Signed64 to Serializer * Added support for Signed64 to Deserializer * Added unit test for ArgMinMax to Deserializer * Deprecated m_Output_Type from the ArgMinMaxDescriptor: the output type is solely determined by the DataType of the output Tensor * Fixed issue where RefArgMinMaxWorkload could output data using the wrong DataType * Added Signed64 to RefLayerSupport::IsArgMinMaxSupported as a supported type Signed-off-by: Mike Kelly <mike.kelly@arm.com> Signed-off-by: Matthew Sloyan <matthew.sloyan@arm.com> Change-Id: Ib622c052a1f8aa3e658262f8bde5a6881a8cbe10
2021-04-08IVGCVSW-5823 Refactor Async Network APIMike Kelly
* Moved IAsyncNetwork into IRuntime. * All LoadedNetworks can be executed Asynchronously. Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: Ibbc901ab9110dc2f881425b75489bccf9ad54169
2021-04-07Fix graph copy memory spikeFinn Williams
* Change layer storage of ConstTensors to std::shared_ptr<ConstCpuTensorHandle> * Change clone to share ConstTensor rather than copy * Remove uses of non-const GetTensor() call * Reduce scope of non-optimized network in ExeNet, so memory can be released after use Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: Ibb2c7309d12411d21405bd6024c76bcdf5404545
2021-04-02IVGCVSW-5783 'Add AsyncExecution Capability'Sadik Armagan
* Added AsyncExecution to the BackendCapability enum class. * Logged a warning if backends do not support AsyncExecution capability if AsyncNetwork is created. Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I49f8467297f4b6b8e414cb6a3638a7d3f1bb886a
2021-03-30IVGCVSW-5799 'Create Pimpl Idiom for Async prototype'Sadik Armagan
* Implemented Pimpl Idiom for IAsyncNetwork Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Ic7311880563568b014a27f6347f8d41f2ad96df6
2021-03-29IVGCVSW-5790 Merge async prototypeMike Kelly
* Added thread safe execution mechanism for armnn * Removed duplicate function bool Compare(T a, T b, float tolerance) * Added StridedSliceAsyncEndToEndTest * Fixed memory leak Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I2d367fc77ee7c01b8953138543e76af5e691211f
2021-03-25IVGCVSW-5736 and IVGCVSW-5743 'NonConstWeights: Update front-end and ↵Sadik Armagan
TfLiteDelegate support for FullyConnected Operator' * Added front-end support for non-const weights for FULLY_CONNECTED operator * Added FULLY_CONNECTED end-to-end test * Updated FULLY_CONNECTED operator support in TfLite Arm NN Delegate for non-const weights * Updated the version numbers Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Iffa5b9aa9297aca4c02d923cce4636c88ac21faa
2021-03-23Revert "Fold PAD into Pooling2d"Jim Flynn
This reverts commit 51ce7d487c761358de105f82ff90553570aedac0. Reason for revert: https://jira.arm.com/browse/IVGCVSW-5798 LargeGraph_TENSOR_FLOAT32 CTS tests failures Change-Id: Ib031a47f605340b2202ecf074ce96a8b54c51075
2021-03-22Fold PAD into Pooling2dDiego Lopez Recas
Some models would add a PAD layer before a pooling when they can't express their padding configuration as SAME or VALID. Arm NN can merge the two because pooling layers are described with explicit padding. Signed-off-by: Diego Lopez Recas <diego.lopez.recas@gmail.com> Change-Id: Id048186db6a005e0257bfbc1406c3b0dab2cdd58
2021-03-16IVGCVSW-5754 Change the behaviour of the AddBroadcastReshapeLayer ↵Finn Williams
Optimisation when the input is a const tensor Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: I8b1357bdefc45880d064d7e448af364ac8644c0d
2021-03-12IVGCVSW-5767 'Regression on SqueezeNet v1.1'Sadik Armagan
* Update ReduceLayer to use descriptor parameters Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I2ff240f63534de0fd647428cf411763829412443
2021-03-03IVGCVSW-5612 Fix tiny_wav2letter_relu_fixed_int8 delegate outputexperimental/abi-testsFinn Williams
* fix delegate perchannel quantization * change delegate to check reshape options before inputs * Add int8 "qsymms8" option to ExecuteNetwork * Add option to run ExecuteNetwork on tflite w/o delegate !referencetests:301301 Signed-off-by: Finn Williams <Finn.Williams@arm.com> Change-Id: If3e12599b17aff1199d7ab0a55e1c901e480083d
2021-03-01Make SubgraphViewSelector give deterministic resultsRob Hughes
The subgraphs produced by SubgraphViewSelector were not deterministic as the order of the input slots, outputs slots and layers within each subgraph were determined by the pointer values of those objects, which are not guaranteed to be the same for each execution. This patch adds a post-processing sorting step based on the GUIDs of the layers and the slot indices so that the results will be the same for each execution. This makes debugging the optimised graph much easier as subsequent stages can also be deterministic. Change-Id: Ifbcb199733066f99e9f95808a8da22023e5944f1 Signed-off-by: Rob Hughes <robert.hughes@arm.com>
2021-02-19Give unique names to debug layersRob Hughes
Debug layers are given names based on the layer they take their input from. If a layer has multiple outputs then one debug layer will be attached to each output. Therefore all these debug layers would have identical names making them hard to distinguish when debugging. This patch includes the output slot index which the debug layer takes its input from when creating the name. Change-Id: I09eaa8a7edad9bfdf678b4778cf740340013126c Signed-off-by: Rob Hughes <robert.hughes@arm.com>
2021-02-17IVGCVSW-5734 Building armnn failed in our Backends CI jobFrancis Murtagh
* CreateTestNetwork() and CreateTransposeTestNetwork should only be defined if Ref enabled; the same as the test its called in otherwise it's defined but not called. Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I7bc522a7884d216d1a8e51afd7cec7a66e4e2947
2021-02-16IVGCVSW-5665 'Basic NN Driver support for next OS Version'Sadik Armagan
Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: If69dbc230e2136def8a697ab25b9c4cb5cb8c731
2021-02-15IVGCVSW-4873 Implement Pimpl Idiom for INetwork and IOptimizedNetworkFrancis Murtagh
!android-nn-driver:5042 Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: Ia1ce8b839e81b46428ba0f78463e085e5906958d Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Signed-off-by: Finn Williams <Finn.Williams@arm.com>
2021-02-15IVGCVSW-5675 Implement Pimpl Idiom for IProfiler (lower priority)Francis Murtagh
Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: If716f5f4e9b5433586b8a939d326830482da2f74
2021-02-12IVGCVSW-4893 Refactor ILayerVisitor using unified interface strategy.Finn Williams
Signed-off-by: Jan Eilers <jan.eilers@arm.com> Signed-off-by: Finn Williams <Finn.Williams@arm.com> Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: Id7bc8255a8e3f9e5aac65d510bec8a559bf37246
2021-02-09MLCE-347 'REDUCE_MIN, REDUCE_MAX, REDUCE_SUM Support'Sadik Armagan
* Added TfLiteParser support for REDUCE_MIN and REDUCE_MAX operators * Added ACL workloads support for REDUCE_MIN, REDUCE_MAX, and REDUCE_SUM operators * Added TfLite Delegate support for REDUCE_MIN, REDUCE_MAX, and REDUCE_SUM operators Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I8085d59946bfd4ab78a59a61f899031ae53371a8
2021-02-08IVGCVSW-4873 Implement Pimpl Idiom for IRuntimeKevin May
Signed-off-by: Kevin May <kevin.may@arm.com> Change-Id: I52448938735b2aa678c47e0f3061c87fa0c693b1
2021-02-05IVGCVSW-4143 Add semantic versioning to Arm NNNikhil Raj
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com> Change-Id: Ibe1200c6d7be9e04821b4a829c83833d44542ad5
2021-02-03backends/reference: Add ReduceSum operation supportSadik Armagan
This patch addes ReduceSum operation support for reference backend, which computes the sum of elements across dimensions of a tensor. Changelog v1: - Fix file header descriptions. Chagelog v2: - Fix line limit issue. - Fix type conversion issue. Changelog v3: - Remove tabs. - Modify newly added file headers. Changelog v4: - Symbol on header isn't allowed so drop it from newly added file headers. Changelog v5: - Remove tabs, fix the use of brackets and align lines correctly. Changelog v6: - Add serializer and deserializer support. Changelog v7: - Fix build error add missed code. Changelog v8: - Rename ReduceSumDecriptor to ReduceDescriptor - Update m_KeepDims field data type to bool on ReduceDescriptor - Add ReduceOperation field to ReduceDescriptor - Rename ReduceSumLayer to ReduceLayer - Update ReduceLayer to use ReduceDescriptor - Update ReduceLayer::ValidateTensorShapesFromInputs() function - Rename RefReduceSumWokload to RefReduceWorkload - Update workload to use ReduceDescriptor - Update workload to use Decoders and Encoders - Remove ReduceSum.hpp and ReduceSum.cpp - Added Reduce.hpp and Reduce.cpp - Move Mean.cpp (which is implementing REDUCE_MEAN) functionality to Reduce.cpp - Update RefMeanWorkload to call Reduce function with ReduceOperation::Mean argument - Remove Mean.hpp and Mean.cpp - Update the Serializer/Deserializer ArmnnSchema.fbs for ReduceLayer, ReduceDescriptor, and ReduceOperation - Update Serializer and Deserializer for serializing/parsing ReduceLayer - Added TfLiter parser Sum test for REDUCE_SUM operator - Make corresponding changes on front-end and Ref backend to support REDUCE_SUM operator Changelog v9: - Fixed build errors. Change-Id: I8c8e034f3df73f9565b3c18eff51ecca6c542195 Signed-off-by: Inki Dae <inki.dae@samsung.com> Signed-off-by: Sadik Armagan <sadik.armagan@arm.com>
2021-01-28IVGCVSW-4874 Provide LayerSupportHandle to frontend usersFrancis Murtagh
* Add test for new IsBackendRegistered member function of Handle * Move deprecated messages to new frontend API of LayerSupportHandle * Update delegate to use dot operator for IsXXXLayerSupported Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: I70d7166e207a10e4b3583a827ca0dda2169bcba1 !android-nn-driver:4940
2021-01-28Remove incorrect use of std::vector.reserveJim Flynn
Change-Id: Ic45d4c837eaad8b9f19288d4f3b6e8caa3eaf319 Signed-off-by: Jim Flynn <jim.flynn@arm.com>
2021-01-25IVGCVSW-5619 Add OptimizerOptions and NetworkProperties to ArmNN DelegateNarumol Prangnawarat
* Add OptimizerOptions, NetworkProperties, DebugCallbackFunction to DelegateOptions * Enable OptimizerOptions when the network is being optimized * Enable NetworkProperties when loading network * Enable DebugCallbackFunction * Add error message when loading network * Log warning instead of error when operator is not supported but could fallback to another backend * Improve uint16_t CompareData * Unit tests Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I353035afb442774bfeb1c62570a90755c2ceaf38
2021-01-25IVGCVSW-5525 Handle Neon optionality on 32 bit linux platformsFrancis Murtagh
* Add neon detection for linux using HWCAPs * Add test to check for backend throwing BackendUnavailable exception Signed-off-by: Francis Murtagh <francis.murtagh@arm.com> Change-Id: Ib74aeb06abe5f88f21ecdd1edb2a1cd20ee2019d
2021-01-14MLCE-325 ArmnnQuantizer incorrectly Quantizes all DataTypesMike Kelly
* ArmnnQuantizer incorrectly converts boolean or integer DataTypes to quantized DataTypes. This breaks layers like ArgMinMax where the output contains the index of an element along an axis. Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I272c3d0f48bf884a2480bfa43eb14ec265fcda6b
2021-01-05adding BOOST_TEST to EnqueueWorkload in FuseActivation Unit TestTeresa Charlin
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I6a00045967fa48ec0913c8708ffc146a72ed2b87
2020-12-17IVGCVSW-5532 Adding UnitTest fusing activationTeresa Charlin
* QASymmS8 and BoundedReLU * Float16 and ReLU in GpuAcc * Remove layerName, not needed as 1 test per combination Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I930c7a04d8d904f370f1b40c62cf9311c172bbdf
2020-12-11Sort subgraphview layers on constructionDerek Lamberti
Make it easier for backends to traverse the subgraph during optimization Change-Id: I140cb11f78bab5f19c801a5b55efffb38c63837f Signed-off-by: Derek Lamberti <derek.lamberti@arm.com>
2020-12-08IVGCVSW-5500 Fix transpose conv InferOutputShapeJames Conroy
* Use kernelShape[0] as channels for outputShape. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: I070c7ff68ae365d9505a5eb28c76f9e52da1e5f9
2020-11-30IVGCVSW-5568 Revert "IVGCVSW-5563 Fix Crash on model with FullyConnected ↵Teresa Charlin
Sigmoid Activation" * This reverts commit be25d94aefe53f221304b1f5f344913b708f808b. * Add Unit Test: any receiver layer + any activation layer in float and QAsymmU8 * Tidy up fuse activation tests Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ie059d03b85cd17eaaafe5188bb173672a1fb9ae0
2020-11-27IVGCVSW-5499 Missing validation for zero strideTeresa Charlin
* Convolution * Depthwise Convolution Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I61b356fbffb176e9a05e08d9b6867d082b6712c8
2020-11-26IVGCVSW-5481 'Add ClCompileContext to ClWorkloadFactory'Sadik Armagan
* Introduced CLCompileContext to ClWorkloadFactory Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: Ied38f4336210502e5f518b9955ae6a5ba3d242b3
2020-11-18Fix logical vts skipNarumol Prangnawarat
* Add Boolean support for Reshape * Use LogicalUnary factory and data type for LogicalNot Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I8e072fde200b7716556ae67f79616458cf98ff20
2020-11-18IVGCVSW-5558 'Output all zeroes using EthosNAcc backend when falling back to ↵Sadik Armagan
CpuRef' Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I0c3ece5baf587e6cc22dfbec7ff98bd3573e0243
2020-11-17IVGCVSW-5535 Extend dump file with info about fused layersMike Kelly
* Add optional ActivationDescriptor information to SerializeLayerParameters Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: I6268932cdc4637cdb30948e1b7f0f0649ba18492
2020-11-17IVGCVSW-5530 'Cannot run SSD Mobilenet f16/uint8 on CpuRef via ExecuteNetwork'Sadik Armagan
* Added FP16 DataType support to DetectionPostProcess * For DetectionPostProcess layer output is always Float32 regardless of input type Signed-off-by: Sadik Armagan <sadik.armagan@arm.com> Change-Id: I21f63dd08f0863e9a98e105b3009bab3da1ab0c3
2020-11-13IVGCVSW-5328-5329 Fuse ActivationMike Kelly
* Added Fused Activation Optimization to both CL and Neon backends. * Added Fused Activation support to all the CL and Neon workloads that support it. * Changed ProfilingTest network to be a Convolution layer followed by an Abs layer rather than an Activation layer. * Added IBackendInternal::OptimizeSubgraphView function that can accept a ModelOptions. * Network will now call OptimizeSubgraphView passing in the ModelOptions. Signed-off-by: Keith Davis <keith.davis@arm.com> Signed-off-by: Mike Kelly <mike.kelly@arm.com> Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: Ib536ac3cbafc7d9b35c139ad9a65b7735262cd9d
2020-11-09IVGCVSW-5091 Add Logical ops frontend and ref implJames Conroy
* Add frontend and reference implementation for logical ops NOT, AND, OR. * Unary NOT uses existing ElementwiseUnary layer and ElementwiseUnary descriptor. * Binary AND/OR uses new layer LogicalBinary and new LogicalBinary descriptor. * Add serialization/deserializion support and add missing ElementwiseUnary deserializer code. * Add additional Boolean decoder in BaseIterator.hpp. Signed-off-by: James Conroy <james.conroy@arm.com> Change-Id: Id343b01174053a166de1b98b6175e04a5065f720
2020-11-09IVGCVSW-5327 Add to Layer a binary blob to host the activation layer infoKeith Davis
Signed-off-by: Keith Davis <keith.davis@arm.com> Change-Id: I0a07dea96a86849701ba387dbea148909a6d729b
2020-11-08IVGCVSW-5315 Create FuseBatchNorm classMike Kelly
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Signed-off-by: Mike Kelly <mike.kelly@arm.com> Change-Id: Id0625c58dbeea79874bf986b70d136ed9390bf83
2020-11-02IVGCVSW-5476 Fix Fuse_batchNorm_into_Conv2D_Float32_TestTeresa Charlin
* failing with no backends provided Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I55ebfc52268ad667e495831c64977338d003db99
2020-10-30Print out more information about the graphAyan Halder
Besides, the layer name, type and backend, it is useful to print the count of input/output tensors. Also, we could print the tensor dimensions. Signed-off-by: Ayan Halder <ayan.halder@arm.com> Change-Id: I91ac09ae1d594e13f01e1db60dc531b16ae87dde
2020-10-30IVGCVSW-5322 Fix segfault between Neon and Cl layersNarumol Prangnawarat
* Fallback to memory copy if memory import is not supported * Remove direct compatibility between Neon and Cl Tensors * Unit tests fallback from Neon to Cl and Cl to Neon Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: Iec00a77423fb23b37a6b1aefee1b2ec4d649efca
2020-10-29IVGCVSW-5468 Rewrite QuantizationDataSet.cpp to avoid use of CsvReaderJames Ward
* Remove armnnUtils/CsvReader and usage * Remove armnn/CsvReaderTest and usage * Replace functionality in QuantizationDataSet.cpp Signed-off-by: James Ward <james.ward@arm.com> Change-Id: I7213904482afa93ae6d607aa5e69117c8c34ea81
2020-10-29IVGCVSW-5314 Create OptimizeForExclusiveConnectionTeresa Charlin
* FuseBatchNorm class has been added to facilitate testing * Only Convolution2D FP32 being fused Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com> Change-Id: I049c4770946ddca21b08516d4c9f4d0d22bf9b45
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