aboutsummaryrefslogtreecommitdiff
path: root/src/armnn/Tensor.cpp
AgeCommit message (Collapse)Author
2020-04-06IVGCVSW-4485 Remove Boost assertNarumol Prangnawarat
* Change boost assert to armnn assert * Change include file to armnn assert * Fix ARMNN_ASSERT_MSG issue with multiple conditions * Change BOOST_ASSERT to BOOST_TEST where appropriate * Remove unused include statements Signed-off-by: Narumol Prangnawarat <narumol.prangnawarat@arm.com> Change-Id: I5d0fa3a37b7c1c921216de68f0073aa34702c9ff
2020-01-24IVGCVSW-4370 Deprecate DataType::QuantizedSymm8PerAxisDerek Lamberti
!android-nn-driver:2622 Change-Id: If99d3eff71ff66ba28af1e5af248299fe04511b9 Signed-off-by: Derek Lamberti <derek.lamberti@arm.com>
2020-01-13Rename quantized data types to remove ambiguity for signed/unsigned payloadsDerek Lamberti
!android-nn-driver:2572 Change-Id: I8fe52ceb09987b3d05c539409510f535165455cc Signed-off-by: Derek Lamberti <derek.lamberti@arm.com>
2019-12-05Replace boost logging with simple loggerDerek Lamberti
!referencetests:214319 * Reduces arm nn binary size ~15% * Also fixed test logging black hole issues Change-Id: Iba27db304d9a8088fa46aeb0b52225d93bb56bc8 Signed-off-by: Derek Lamberti <derek.lamberti@arm.com>
2019-11-06IVGCVSW-3837 Add support for per-axis quantization to reference ↵Aron Virginas-Tar
Convolution2d workload Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: I0ac08ba4864d48e6f64c4ac645dad8ea850be112
2019-10-30IVGCVSW-3831 Add support of per-axis quantization to TensorInfoAron Virginas-Tar
Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com> Change-Id: Iea09539c92d51e546fbad8b2903b59fc08d66618
2019-04-16IVGCVSW-2957 MergerLayer subtensor optimization now backend agnosticDerek Lamberti
+ Update clframework pin + Cl and Neon Merger workloads updated to use MemoryLayout agnostic API + Workloads only use sub-tensor optimization if ALL input tensors are sub-tensors + Refactor LayerSupportCommon code to be a bit more succinct Change-Id: Ib61ad4ccbd767e924dff07e61022e0cda4069828 Signed-off-by: Derek Lamberti <derek.lamberti@arm.com>
2019-02-22IVGCVSW-2749 Throw exception in TensorShape when requested index >= number ↵Aron Virginas-Tar
of dimensions Change-Id: I3589b1e901b0f81f6bb17848046a22829f91bb9e Signed-off-by: Aron Virginas-Tar <Aron.Virginas-Tar@arm.com>
2018-12-07IVGCVSW-2268 Remove the input swizzling from ParseConcatMatteo Martincigh
* Removed the input swizzling when the concatenation dimension is 3 in ParseConcat in the TF parser * No longer using the helper ProcessConcatInputTensorInfo, where the input was being swizzled if the concatenation dimension was 3 * Added a new convenience constuctor to TensorShape that initializes a shape to all zeros given only the number of dimensions Change-Id: I82a207e41bddc5fea21a0b5a38eafa24ad75d1c2
2018-09-17IVGCVSW-1807 : change license text in file headersDavid Beck
All changes are the same: // // Copyright © 2017 ARM Ltd. All rights reserved. -// See LICENSE file in the project root for full license information. +// SPDX-License-Identifier: MIT // Change-Id: I37eae011411133663ca9d2b059714d92f8bf8e24
2018-08-31Release 18.08telsoa01
2018-03-09Release 18.02telsoa01
Change-Id: Id3c11dc5ee94ef664374a988fcc6901e9a232fa6
generated by cgit v1.2.1 (git 2.23.0) at 2024-06-26 17:45:54 +0000