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* Resolves: IVGCVSW-6952
Signed-off-by: Finn Williams <finn.williams@arm.com>
Change-Id: Ic85bd5267cf94e0ee8461ff4e62b9db3cb80877a
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* Signature change is ABI/API break, overloaded and forwarded to new function.
Signed-off-by: Francis Murtagh <francis.murtagh@arm.com>
Change-Id: I8590a6fd65986b5aeff905c1e761cb5c51042e99
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!android-nn-driver:7477
Signed-off-by: Cathal Corbett <cathal.corbett@arm.com>
Change-Id: Ibf633ccccc385bd980934ff829407d21981323ef
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Remove use of std::unary_function and std::binary_function which were
deprecated in C+11.
Signed-off-by: Matthew Bentham <matthew.bentham@arm.com>
Change-Id: I9e4624f570b475595c9e28bdf185ddcc2ddceb2f
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* Update Front-end and Tools.
* Updated Serializer, Deserializer and unit tests to reflect this.
* Updated TfLiteDelegate, TfLiteParser and OnnxParser.
* Updated Ref.
* Fixed resulting Neon / CL tests
* Unified optimizers for conv2d ops
* Optimizer Fix - Fp32ToBf16
* Partial implementation for ACL backends to fix VTS failures
!android-nn-driver:7477
Signed-off-by: Keith Davis <keith.davis@arm.com>
Change-Id: I5fb18877f7ee32643e15a9818945356274bb401b
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Signed-off-by: Nikhil Raj <nikhil.raj@arm.com>
Change-Id: I8d1584478983aeb68f65739a9ad3d4e5d3573a5c
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* Add IsSupported for Pooling3d
* Add CreateWorkload case for Pooling3d
* Create new NeonPooling3dWorkload header and source files
* Add Pooling3d workload to NeonWorkloads.hpp
* Add float32 tests for Pooling3d workload
* Add Uint8 tests for Cl and NE pooling3d
Signed-off-by: Ryan OShea <ryan.oshea3@arm.com>
Change-Id: Ic992e1233d1eb8db52df2c8446183df1c907bc4d
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* IVGCVSW-6940 ConstTensorsAsInput: DepthwiseConvolution2d - Complete Neon and Cl Bug Fix
* Bug fix to enable Cl and Neon Backend Compatibility ConstantTensorsAsInputs
* Updated Cl and Neon FullyConnected workloads to handle constant
weights and bias as inputs rather than reading from member variables.
* Prevent non const weights and biases passing CL and NEON validate
for Depthwise Convolution.
Signed-off-by: Cathal Corbett <cathal.corbett@arm.com>
Change-Id: I0f505ff5998a183152f843d0f6cc74327ba920e7
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Change-Id: I2c23a8d7173b07aa8797a771489599762cba5a16
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
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* Added backend specific optimization & test for CpuAcc and GpuAcc: PermuteDepthwiseConv2dWeights
Signed-off-by: Cathal Corbett <cathal.corbett@arm.com>
Change-Id: I600476b2e9c557a39818a574c1091c9d650b21b1
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* Addressing unresolved comment.
Signed-off-by: Cathal Corbett <cathal.corbett@arm.com>
Change-Id: Ia70999582670f2b521e9e2c891831618e476024f
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* Fixes Segmentation fault in RefDepthwiseConvolution2d workload
originated by IVGCVSW-6127 ConstTensorsAsInput DepthwiseConvolution2d
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I019377777ae384bcd193ecab7b8cdf8266e79f45
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* Add Unit Tests
* Bug Fix: add Sqrt to Neon and Cl workload factories
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I0db1d813a4e7d15431e87e825e6d14e61f5ffb7d
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Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I8ba7e56062c285c672dcaa9d13be319eb4f1fca6
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Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I6b1c7c1c499dc93aa58fa9f58b64fb664e8bcc56
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* It's possible that a model may have an input entry for bias tensors
but that the index for those is -1. If it's -1 then it's not present.
* Fixed logic error in IsOptionalOperandPresent: it returned false if
it was present and true if it was missing.
Signed-off-by: Mike Kelly <mike.kelly@arm.com>
Change-Id: I45ad8d8552122493c529b1a35a5689416ccfbb71
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valid from IVGCVSW-4449
* Github issue: https://github.com/ARM-software/armnn/issues/639
Signed-off-by: Cathal Corbett <cathal.corbett@arm.com>
Change-Id: If93f2cae101814652664c671417946b94a9f749c
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Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: Ib90bade63cd0437329c690b09cf719a2e2bd06a4
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* Add validate for all layers for GatherNd
* Fix convert policy for Mul
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I0f2bae5107607ba3c02b5546f60dd9623cd95853
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Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I195957541069cb52cdd2c8aead0e4a34498a6f38
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!android-nn-driver:7418
* Update Front-end and Tools.
* Updated Serializer, Deserializer and unit tests to reflect this.
* Updated TfLiteDelegate, TfLiteParser and OnnxParser.
* Change NNDriver to new API.
* Updated Ref.
* Neon and Cl backend partially completed (Backend.cpp files).
* Added dynamic or constant input EndToEnd tests.
* Added ConstantTensorAsInputMemeberVariableRedirect Optimization.
Signed-off-by: Cathal Corbett <cathal.corbett@arm.com>
Change-Id: Ib18b6c10a093042e165e25237dc04a4c67ba82da
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This reverts commit 38b72e8de898d84a1481e242803da61009719891.
* It is not longer needed as this functionality is cover with the commit:
IVGCVSW-6938 Do not add Floor when FloorDiv is int32 in Tfliteparser
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: Iac757cf9b47d2516804dca2efb347cfbd3282f14
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Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I7ce633a66e2ecb72a9cdd1bff690c4195a9a449f
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* Changing the test in the delegate to match one of the unit tests
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I553ca266116ba8ee173fc951ab1ffd2b6eed1428
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* Corrected TensorInfo order for IsUnidirectionalSequenceLstmSupported
* outputStateOut TensorInfo is not optional.
* cellStateOut TensorInfo is not optional.
* TensorInfo Order matches other QLSTM/LSTM layers.
* Added missing parameters to UnidirectionalSequenceLstmOperator for
delegate.
* Added quantized UnidirectionalSequenceLstm support to Neon
!android-nn-driver:7457
Signed-off-by: Mike Kelly <mike.kelly@arm.com>
Change-Id: I26dde1bb96793dd25eb9081ca5ae5f63752288c4
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* Added building flatbuffer section
* Added installing cmake 3.19
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com>
Change-Id: I35925a1dc3c1fdcf3c7b7a1d44f24bd3253c9159
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Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I6f7cddb2d23c67ae682132d18f98776c074dcb3b
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Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I3b1f44c10a3446cfe45a7757d8a98e9788ec5dc0
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Signed-off-by: Nikhil Raj <nikhil.raj@arm.com>
Change-Id: I5c314213d3ac4fe150b0ea41cc9117add7654e50
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Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I7c80299f539b64682a6a68cd1709089f71600cd9
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Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I56418875b3bb2ae45b5c69bfeaafa1a6126b8085
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Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I8142072f104b23c6eaf80b54cf6ddfa0393c4921
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Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: Ibab3525d53edbdf6a48e43b2bf668fcd2efaba58
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* Add front end
* Add reference workload
* Add unit tests
* Add EndToEnd test
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I4cebd17b18476df86162e2dda3366c10e80bd2f8
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* Fix shellcheck warnings, some have been
suppressed using shellcheck ignore.
Change-Id: Icae175a42bb348a58befb296949edca51713e977
Signed-off-by: James Conroy <james.conroy@arm.com>
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Signed-off-by: Jim Flynn <jim.flynn@arm.com>
Change-Id: Ic7a1cd6e03d4a2c6a717323469d429ca6cb2c914
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* Update more-itertools to 8.12
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com>
Change-Id: I572340793db0e7da993679466d723c61d6d2bab2
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* Update Neon pooling kernel
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com>
Change-Id: I2d2028b29c69156133d42832a6f8e7e2de7d4363
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* [CpuGemmConv2d] Extract skip_im2col and skip_col2im computation.
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I45ef95e33d8803df6147b7437918151bf67be611
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* Added Unidirectional Sequence Lstm support to TFLite Parser
* Added support for float operations with int8 weights to TFLite Parser
* Added to Conv2d, Conv3D, DepthwiseConv2D, FullyConnected,
TransposeConv and UnidirectionalSequenceLstm
* Renamed subgraphIndex to subgraph to fix name-shadowing warning.
Signed-off-by: Mike Kelly <mike.kelly@arm.com>
Change-Id: I818976ab88abc05dcb4bad246fb4108e6e879283
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# Fix Duplicate Template in Pooling3dFixture
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: Ibc92cdf0af6e173005e9d093a301591df126b21e
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* Use read() to load model from disk
Signed-off-by: Simon Obute <simon.obute@arm.com>
Change-Id: I0321fa7716e1887b59063429da7e5a2e66aebe83
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# Add CLPool3d Int8 Support
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: Ib5d27bcd55f00c786f8e50ad02b912f62b417a80
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Signed-off-by: Elham <elham.harirpoush@arm.com>
Change-Id: Idc03badf532918925fc59db81a7affab439075f1
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#Enable dynamic cl tuning for dynamically fused kernels
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: Ia398fae766a64216d5ad7ad2d801260dfe836892
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Change-Id: Ice69c2a22f589f68d302f80500dfe4e514a796d2
Signed-off-by: Jim Flynn <jim.flynn@arm.com>
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# Add documentations about compiler_prefix and toolchain_prefix
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I49b058913e9ab85e6765d9b5b87f7394174a6127
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Signed-off-by: Raviv Shalev <raviv.shalev@arm.com>
Change-Id: I25fcccbf912be0c5bd4fbfd2e97552341958af35
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Signed-off-by: Dvir Markovich <dvir.markovich@arm.com>
Change-Id: If412c15ba49abe8370a570260b0a8ed8de305b7c
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* Add IsSupported for Pooling3d
* Add CreateWorkload case for Pooling3d
* Create new ClPooling3dWorkload header and source files
* Add Pooling3d workload to ClWorkloads.hpp
* Add tests for Pooling3d workload
* Add Pooling3d build function to ArmComputeTensorUtils
Change-Id: Ia270b0fe809a171ed73af14376de8708b346d500
Signed-off-by: Ryan OShea <ryan.oshea3@arm.com>
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