6 files changed, 118 insertions, 0 deletions
diff --git a/src/backends/reference/workloads/CMakeLists.txt b/src/backends/reference/workloads/CMakeLists.txt
index 1ab38ccbcb..db0daa0310 100644
--- a/src/backends/reference/workloads/CMakeLists.txt
+++ b/src/backends/reference/workloads/CMakeLists.txt
@@ -36,6 +36,8 @@ list(APPEND armnnRefBackendWorkloads_sources
     Pad.hpp
     Pooling2d.cpp
     Pooling2d.hpp
+    PreluImpl.cpp
+    PreluImpl.hpp
     RefActivationWorkload.cpp
     RefActivationWorkload.hpp
     RefBatchNormalizationWorkload.cpp
@@ -84,6 +86,8 @@ list(APPEND armnnRefBackendWorkloads_sources
     RefPermuteWorkload.hpp
     RefPooling2dWorkload.cpp
     RefPooling2dWorkload.hpp
+    RefPreluWorkload.cpp
+    RefPreluWorkload.hpp
     RefQuantizeWorkload.cpp
     RefQuantizeWorkload.hpp
     RefReshapeWorkload.cpp
diff --git a/src/backends/reference/workloads/PreluImpl.cpp b/src/backends/reference/workloads/PreluImpl.cpp
new file mode 100644
index 0000000000..458025bb0a
--- /dev/null
+++ b/src/backends/reference/workloads/PreluImpl.cpp
@@ -0,0 +1,35 @@
+//
+// Copyright © 2017 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "PreluImpl.hpp"
+#include "RefWorkloadUtils.hpp"
+#include "Broadcast.hpp"
+
+namespace armnn
+{
+
+void PreluImpl(const PreluQueueDescriptor& data,
+               Decoder<float>& inputData,
+               Decoder<float>& alphaData,
+               Encoder<float>& outputData)
+{
+    const TensorInfo& inputInfo  = GetTensorInfo(data.m_Inputs[0]);
+    const TensorInfo& alphaInfo  = GetTensorInfo(data.m_Inputs[1]);
+    const TensorInfo& outputInfo = GetTensorInfo(data.m_Outputs[0]);
+
+    const TensorShape& inputShape  = inputInfo.GetShape();
+    const TensorShape& alphaShape  = alphaInfo.GetShape();
+    const TensorShape& outputShape = outputInfo.GetShape();
+
+    // PReLU activation: f(x) = alpha * x for x < 0, f(x) = x for x >= 0
+    auto prelu = [](float x, float alpha)
+    {
+        return x < 0 ? alpha * x : x;
+    };
+
+    BroadcastLoop(inputShape, alphaShape, outputShape).Unroll(prelu, 0, inputData, alphaData, outputData);
+}
+
+} // namespace armnn
diff --git a/src/backends/reference/workloads/PreluImpl.hpp b/src/backends/reference/workloads/PreluImpl.hpp
new file mode 100644
index 0000000000..9299b1c7f7
--- /dev/null
+++ b/src/backends/reference/workloads/PreluImpl.hpp
@@ -0,0 +1,21 @@
+//
+// Copyright © 2017 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include "Encoders.hpp"
+#include "Decoders.hpp"
+
+#include <backendsCommon/WorkloadData.hpp>
+
+namespace armnn
+{
+
+void PreluImpl(const PreluQueueDescriptor& data,
+               Decoder<float>& inputData,
+               Decoder<float>& alphaData,
+               Encoder<float>& outputData);
+
+} // namespace armnn
diff --git a/src/backends/reference/workloads/RefPreluWorkload.cpp b/src/backends/reference/workloads/RefPreluWorkload.cpp
new file mode 100644
index 0000000000..cdc0a63711
--- /dev/null
+++ b/src/backends/reference/workloads/RefPreluWorkload.cpp
@@ -0,0 +1,35 @@
+//
+// Copyright © 2017 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "RefPreluWorkload.hpp"
+
+#include "RefWorkloadUtils.hpp"
+#include "PreluImpl.hpp"
+
+#include <Profiling.hpp>
+
+namespace armnn
+{
+
+RefPreluWorkload::RefPreluWorkload(const PreluQueueDescriptor& descriptor,
+                                   const WorkloadInfo& info)
+    : BaseWorkload(descriptor, info)
+{}
+
+void RefPreluWorkload::Execute() const
+{
+    ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefPreluWorkload_Execute");
+
+    std::unique_ptr<Decoder<float>> inputDecoder = MakeDecoder<float>(GetTensorInfo(m_Data.m_Inputs[0]),
+                                                                      m_Data.m_Inputs[0]->Map());
+    std::unique_ptr<Decoder<float>> alphaDecoder = MakeDecoder<float>(GetTensorInfo(m_Data.m_Inputs[1]),
+                                                                      m_Data.m_Inputs[1]->Map());
+    std::unique_ptr<Encoder<float>> outputEncoder = MakeEncoder<float>(GetTensorInfo(m_Data.m_Outputs[0]),
+                                                                       m_Data.m_Outputs[0]->Map());
+
+    PreluImpl(m_Data, *inputDecoder, *alphaDecoder, *outputEncoder);
+}
+
+} // namespace armnn
diff --git a/src/backends/reference/workloads/RefPreluWorkload.hpp b/src/backends/reference/workloads/RefPreluWorkload.hpp
new file mode 100644
index 0000000000..72839e67dc
--- /dev/null
+++ b/src/backends/reference/workloads/RefPreluWorkload.hpp
@@ -0,0 +1,22 @@
+//
+// Copyright © 2017 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include <backendsCommon/Workload.hpp>
+#include <backendsCommon/WorkloadData.hpp>
+
+namespace armnn
+{
+
+class RefPreluWorkload : public BaseWorkload<PreluQueueDescriptor>
+{
+public:
+    explicit RefPreluWorkload(const PreluQueueDescriptor& descriptor,
+                              const WorkloadInfo& info);
+    virtual void Execute() const override;
+};
+
+} // namespace armnn
diff --git a/src/backends/reference/workloads/RefWorkloads.hpp b/src/backends/reference/workloads/RefWorkloads.hpp
index b14129146a..41b16fa56f 100644
--- a/src/backends/reference/workloads/RefWorkloads.hpp
+++ b/src/backends/reference/workloads/RefWorkloads.hpp
@@ -51,3 +51,4 @@
 #include "RefDequantizeWorkload.hpp"
 #include "RefQuantizeWorkload.hpp"
 #include "RefReshapeWorkload.hpp"
+#include "RefPreluWorkload.hpp"