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author | Nikhil Raj <nikhil.raj@arm.com> | 2018-10-12 13:51:57 +0100 |
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committer | Matthew Bentham <matthew.bentham@arm.com> | 2018-10-22 16:57:53 +0100 |
commit | cec6b655d9f6ddb73c721ca47a7d67eeaad5c043 (patch) | |
tree | 898dbc90785f77f9c724bb8de61d7fb1b1ce3c0b /src/backends/test | |
parent | f3eb46d23c6001150d36d80acac7ad1247174630 (diff) | |
download | armnn-cec6b655d9f6ddb73c721ca47a7d67eeaad5c043.tar.gz |
IVGCVSW-1922 Unit test for DepthwiseConvolution with NHWC
Change-Id: I3e6e5b9a62f30d03c05bd7178adea8f4c8275da8
Diffstat (limited to 'src/backends/test')
-rwxr-xr-x[-rw-r--r--] | src/backends/test/Conv2dTestImpl.hpp | 100 | ||||
-rwxr-xr-x[-rw-r--r--] | src/backends/test/LayerTests.cpp | 119 | ||||
-rw-r--r-- | src/backends/test/LayerTests.hpp | 3 |
3 files changed, 222 insertions, 0 deletions
diff --git a/src/backends/test/Conv2dTestImpl.hpp b/src/backends/test/Conv2dTestImpl.hpp index 8e29615c47..d8c104007c 100644..100755 --- a/src/backends/test/Conv2dTestImpl.hpp +++ b/src/backends/test/Conv2dTestImpl.hpp @@ -691,6 +691,106 @@ LayerTestResult<T, 4> DepthwiseConvolution2dTestImpl(armnn::IWorkloadFactory& wo return ret; } +template<typename T, typename B> +LayerTestResult<T, 4> DepthwiseConvolution2dNhwcTestImpl(armnn::IWorkloadFactory& workloadFactory, + const boost::multi_array<T, 4>& input, + const boost::multi_array<T, 4>& kernel, + const boost::multi_array<B, 1>& bias, + const boost::multi_array<T, 4>& outputExpected, + float qScale, + int32_t qOffset, + uint32_t padLeft = 0, + uint32_t padTop = 0, + uint32_t padRight = 0, + uint32_t padBottom = 0, + uint32_t strideX = 1, + uint32_t strideY = 1) +{ + unsigned int inputNum = boost::numeric_cast<unsigned int>(input.shape()[0]); + unsigned int inputChannels = boost::numeric_cast<unsigned int>(input.shape()[3]); + unsigned int inputHeight = boost::numeric_cast<unsigned int>(input.shape()[1]); + unsigned int inputWidth = boost::numeric_cast<unsigned int>(input.shape()[2]); + + unsigned int kernelChanMul = boost::numeric_cast<unsigned int>(kernel.shape()[0]); + unsigned int kernelChannels = boost::numeric_cast<unsigned int>(kernel.shape()[3]); + unsigned int kernelHeight = boost::numeric_cast<unsigned int>(kernel.shape()[1]); + unsigned int kernelWidth = boost::numeric_cast<unsigned int>(kernel.shape()[2]); + + unsigned int outputNum = boost::numeric_cast<unsigned int>(outputExpected.shape()[0]); + unsigned int outputChannels = boost::numeric_cast<unsigned int>(outputExpected.shape()[3]); + unsigned int outputHeight = boost::numeric_cast<unsigned int>(outputExpected.shape()[1]); + unsigned int outputWidth = boost::numeric_cast<unsigned int>(outputExpected.shape()[2]); + + // Creates the tensors. + armnn::TensorInfo inputTensorInfo({inputNum, inputHeight, inputWidth, inputChannels}, armnn::GetDataType<T>()); + armnn::TensorInfo outputTensorInfo({outputNum, outputHeight, outputWidth, outputChannels}, + armnn::GetDataType<T>()); + armnn::TensorInfo kernelDesc({kernelChanMul, kernelHeight, kernelWidth, kernelChannels}, armnn::GetDataType<T>()); + armnn::TensorInfo biasDesc({static_cast<unsigned int>(bias.size())}, armnn::GetDataType<B>()); + + // Set quantization parameters if the requested type is a quantized type. + if (armnn::IsQuantizedType<T>()) + { + inputTensorInfo.SetQuantizationScale(qScale); + inputTensorInfo.SetQuantizationOffset(qOffset); + outputTensorInfo.SetQuantizationScale(qScale); + outputTensorInfo.SetQuantizationOffset(qOffset); + kernelDesc.SetQuantizationScale(qScale); + kernelDesc.SetQuantizationOffset(qOffset); + biasDesc.SetQuantizationScale(qScale*qScale); + biasDesc.SetQuantizationOffset(0); + } + + // Construct the input data. + std::vector<T> inputData; + inputData.assign(input.data(), input.data() + inputHeight*inputWidth*inputChannels); + auto batchedInput = MakeTensor<T, 4>(inputTensorInfo, inputData); + + // Construct the output data, with bias applied, as appropriate. + std::vector<T> outputData; + outputData.assign(outputExpected.data(), outputExpected.data() + outputHeight*outputWidth*outputChannels); + + LayerTestResult<T, 4> ret(outputTensorInfo); + ret.outputExpected = MakeTensor<T, 4>(outputTensorInfo, outputData); + + std::unique_ptr<armnn::ITensorHandle> inputHandle = workloadFactory.CreateTensorHandle(inputTensorInfo); + std::unique_ptr<armnn::ITensorHandle> outputHandle = workloadFactory.CreateTensorHandle(outputTensorInfo); + + armnn::ScopedCpuTensorHandle weightsTensor(kernelDesc); + AllocateAndCopyDataToITensorHandle(&weightsTensor, &kernel[0][0][0][0]); + + armnn::ScopedCpuTensorHandle biasTensor(biasDesc); + + armnn::DepthwiseConvolution2dQueueDescriptor data; + data.m_Weight = &weightsTensor; + data.m_Bias = &biasTensor; // Still set this whether or not bias is enabled - it can be a source of bugs. + data.m_Parameters.m_StrideX = strideX; + data.m_Parameters.m_StrideY = strideY; + data.m_Parameters.m_PadLeft = padLeft; + data.m_Parameters.m_PadRight = padRight; + data.m_Parameters.m_PadTop = padTop; + data.m_Parameters.m_PadBottom = padBottom; + data.m_Parameters.m_DataLayout = armnn::DataLayout::NHWC; + + armnn::WorkloadInfo info; + AddInputToWorkload(data, info, inputTensorInfo, inputHandle.get()); + AddOutputToWorkload(data, info, outputTensorInfo, outputHandle.get()); + + std::unique_ptr<armnn::IWorkload> workload = workloadFactory.CreateDepthwiseConvolution2d(data, info); + + inputHandle->Allocate(); + outputHandle->Allocate(); + + CopyDataToITensorHandle(inputHandle.get(), &batchedInput[0][0][0][0]); + + workloadFactory.Finalize(); + workload->Execute(); + + CopyDataFromITensorHandle(&ret.output[0][0][0][0], outputHandle.get()); + + return ret; +} + template<typename T> LayerTestResult<T,4> Convolution1dTestImpl(armnn::IWorkloadFactory& workloadFactory, float qScale, diff --git a/src/backends/test/LayerTests.cpp b/src/backends/test/LayerTests.cpp index d5f84f0920..f2bc0192ba 100644..100755 --- a/src/backends/test/LayerTests.cpp +++ b/src/backends/test/LayerTests.cpp @@ -493,6 +493,119 @@ LayerTestResult<T, 4> DepthwiseConvolution2dAsymmetricTestCommon(armnn::IWorkloa 1); // strideY } +template<typename T> +LayerTestResult<T, 4> DepthwiseConvolution2dNhwcTestCommon(armnn::IWorkloadFactory& workloadFactory, + float qScale, + int32_t qOffset, + bool biasEnabled) +{ + armnn::TensorInfo inputTensorInfo({ 1, 5, 5, 2}, armnn::GetDataType<T>()); + auto input = MakeTensor<T, 4>(inputTensorInfo, std::vector<T>( + QuantizedVector<T>(inputTensorInfo.GetQuantizationScale(), inputTensorInfo.GetQuantizationOffset(), { + 0, 25, + 1, 26, + 2, 27, + 3, 28, + 4, 29, + + 5, 30, + 6, 31, + 7, 32, + 8, 33, + 9, 34, + + 10, 35, + 11, 36, + 12, 37, + 13, 38, + 14, 39, + + 15, 40, + 16, 41, + 17, 42, + 18, 43, + 19, 44, + + 20, 45, + 21, 46, + 22, 47, + 23, 48, + 24, 49 + }))); + + armnn::TensorInfo kernelTensorInfo({ 1, 4, 4, 2}, armnn::GetDataType<T>()); + auto kernel = MakeTensor<T, 4>(kernelTensorInfo, std::vector<T>( + QuantizedVector<T>(kernelTensorInfo.GetQuantizationScale(), kernelTensorInfo.GetQuantizationOffset(), { + 32, 16, + 31, 15, + 30, 14, + 29, 13, + + 28, 12, + 27, 11, + 26, 10, + 25, 9, + + 24, 8, + 23, 7, + 22, 6, + 21, 5, + + 20, 4, + 19, 3, + 18, 2, + 17, 1 + }))); + + armnn::TensorInfo outputTensorInfo({ 1, 5, 5, 2}, armnn::GetDataType<T>()); + boost::multi_array<T, 4> expectedOutput = MakeTensor<T, 4>(outputTensorInfo, std::vector<T>( + QuantizedVector<T>(outputTensorInfo.GetQuantizationScale(), outputTensorInfo.GetQuantizationOffset(), { + 1062, 1550, + 1580, 2284, + 1850, 2362, + 1530, 1955, + 1117, 1428, + + 2140, 2910, + 3108, 4206, + 3500, 4342, + 2842, 3528, + 2042, 2536, + + 3580, 3390, + 5068, 4886, + 5460, 5022, + 4342, 4068, + 3062, 2916, + + 3618, 3566, + 5072, 5056, + 5390, 5182, + 4248, 4133, + 2971, 2922, + + 3074, 3100, + 4282, 4352, + 4510, 4452, + 3533, 3517, + 2457, 2465 + }))); + + return DepthwiseConvolution2dNhwcTestImpl<T>(workloadFactory, + input, + kernel, + GetBias2<typename FullyConnectedBiasTypeForInputType<T>::Type>(biasEnabled, qScale, qOffset), + expectedOutput, + qScale, + qOffset, + 1, // Padding left. + 1, // Padding top. + 2, // Padding right. + 2, // Padding bottom. + 1, // strideX + 1); // strideY +} + LayerTestResult<float, 4> Convolution2dAsymmetricPaddingLargerThanHalfKernelSizeTest(armnn::IWorkloadFactory& workloadFactory) { @@ -510,6 +623,12 @@ LayerTestResult<float, 4> DepthwiseConvolution2dTest(armnn::IWorkloadFactory& wo return DepthwiseConvolution2dTestImpl<float, float>(workloadFactory, 0.0f, 0, biasEnabled); } +LayerTestResult<float, 4> DepthwiseConvolution2dDepthNhwcTest(armnn::IWorkloadFactory& workloadFactory, + bool biasEnabled) +{ + return DepthwiseConvolution2dNhwcTestCommon<float>(workloadFactory, 0.0f, 0, biasEnabled); +} + LayerTestResult<float, 4> DepthwiseConvolution2dDepthMul1Test(armnn::IWorkloadFactory& workloadFactory, bool biasEnabled) { diff --git a/src/backends/test/LayerTests.hpp b/src/backends/test/LayerTests.hpp index f5abd985c8..9f8cd3ff25 100644 --- a/src/backends/test/LayerTests.hpp +++ b/src/backends/test/LayerTests.hpp @@ -68,6 +68,9 @@ LayerTestResult<uint8_t, 4> Convolution1dUint8Test(armnn::IWorkloadFactory& work LayerTestResult<float, 4> DepthwiseConvolution2dTest(armnn::IWorkloadFactory& workloadFactory, bool biasEnabled); +LayerTestResult<float, 4> DepthwiseConvolution2dDepthNhwcTest(armnn::IWorkloadFactory& workloadFactory, + bool biasEnabled); + LayerTestResult<float, 4> DepthwiseConvolution2dDepthMul1Test(armnn::IWorkloadFactory& workloadFactory, bool biasEnabled); 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