IVGCVSW-3723 Adding reference workload support for ArgMinMax

Change-Id: I65209ecec4e3abf808163239748d6e830568c2e3
Signed-off-by: Nikhil Raj <nikhil.raj@arm.com>

4 files changed, 65 insertions, 0 deletions

diff --git a/src/backends/reference/workloads/CMakeLists.txt b/src/backends/reference/workloads/CMakeLists.txt
index 30770956ba..83444eda1f 100644
--- a/src/backends/reference/workloads/CMakeLists.txt
+++ b/src/backends/reference/workloads/CMakeLists.txt
@@ -6,6 +6,8 @@
 list(APPEND armnnRefBackendWorkloads_sources
     Abs.cpp
     Abs.hpp
+    ArgMinMax.cpp
+    ArgMinMax.hpp
     Activation.cpp
     Activation.hpp
     ArgMinMax.cpp
@@ -49,6 +51,8 @@ list(APPEND armnnRefBackendWorkloads_sources
     RefAbsWorkload.hpp
     RefActivationWorkload.cpp
     RefActivationWorkload.hpp
+    RefArgMinMaxWorkload.cpp
+    RefArgMinMaxWorkload.hpp
     RefBatchNormalizationWorkload.cpp
     RefBatchNormalizationWorkload.hpp
     RefBatchToSpaceNdWorkload.cpp
diff --git a/src/backends/reference/workloads/RefArgMinMaxWorkload.cpp b/src/backends/reference/workloads/RefArgMinMaxWorkload.cpp
new file mode 100644
index 0000000000..5f1eb73b61
--- /dev/null
+++ b/src/backends/reference/workloads/RefArgMinMaxWorkload.cpp
@@ -0,0 +1,38 @@
+//
+// Copyright © 2019 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#include "RefArgMinMaxWorkload.hpp"
+
+#include "ArgMinMax.hpp"
+#include "RefWorkloadUtils.hpp"
+#include "Decoders.hpp"
+#include "Encoders.hpp"
+#include "Profiling.hpp"
+
+namespace armnn
+{
+RefArgMinMaxWorkload::RefArgMinMaxWorkload(
+        const ArgMinMaxQueueDescriptor& descriptor,
+        const WorkloadInfo& info)
+        : BaseWorkload<ArgMinMaxQueueDescriptor>(descriptor, info) {}
+
+void RefArgMinMaxWorkload::Execute() const
+{
+    ARMNN_SCOPED_PROFILING_EVENT(Compute::CpuRef, "RefArgMinMaxWorkload_Execute");
+
+    const TensorInfo &inputTensorInfo = GetTensorInfo(m_Data.m_Inputs[0]);
+
+    std::unique_ptr<Decoder<float>> decoderPtr = MakeDecoder<float>(inputTensorInfo, m_Data.m_Inputs[0]->Map());
+    Decoder<float> &decoder = *decoderPtr;
+
+    const TensorInfo &outputTensorInfo = GetTensorInfo(m_Data.m_Outputs[0]);
+
+    int32_t* output = GetOutputTensorData<int32_t>(0, m_Data);
+
+    ArgMinMax(decoder, output, inputTensorInfo, outputTensorInfo, m_Data.m_Parameters.m_Function,
+              m_Data.m_Parameters.m_Axis);
+}
+
+} //namespace armnn
\ No newline at end of file
diff --git a/src/backends/reference/workloads/RefArgMinMaxWorkload.hpp b/src/backends/reference/workloads/RefArgMinMaxWorkload.hpp
new file mode 100644
index 0000000000..97b70772d1
--- /dev/null
+++ b/src/backends/reference/workloads/RefArgMinMaxWorkload.hpp
@@ -0,0 +1,21 @@
+//
+// Copyright © 2019 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+
+#pragma once
+
+#include <backendsCommon/Workload.hpp>
+#include <backendsCommon/WorkloadData.hpp>
+
+namespace armnn
+{
+class RefArgMinMaxWorkload : public BaseWorkload<ArgMinMaxQueueDescriptor>
+{
+public:
+    explicit RefArgMinMaxWorkload(const ArgMinMaxQueueDescriptor& descriptor,
+                                  const WorkloadInfo& info);
+
+    virtual void Execute() const override;
+};
+} //namespace armnn
\ No newline at end of file
diff --git a/src/backends/reference/workloads/RefWorkloads.hpp b/src/backends/reference/workloads/RefWorkloads.hpp
index 959226adf6..b4721b11aa 100644
--- a/src/backends/reference/workloads/RefWorkloads.hpp
+++ b/src/backends/reference/workloads/RefWorkloads.hpp
@@ -7,6 +7,7 @@
 
 #include "Abs.hpp"
 #include "Activation.hpp"
+#include "ArgMinMax.hpp"
 #include "BatchNormImpl.hpp"
 #include "ConvImpl.hpp"
 #include "Concatenate.hpp"
@@ -16,6 +17,7 @@
 #include "Pooling2d.hpp"
 #include "RefAbsWorkload.hpp"
 #include "RefActivationWorkload.hpp"
+#include "RefArgMinMaxWorkload.hpp"
 #include "RefBatchNormalizationWorkload.hpp"
 #include "RefBatchToSpaceNdWorkload.hpp"
 #include "RefConvolution2dWorkload.hpp"