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| author | Francis Murtagh <francis.murtagh@arm.com> | 2019-06-24 14:24:36 +0100 |
|---|---|---|
| committer | Matthew Bentham <matthew.bentham@arm.com> | 2019-06-25 08:48:10 +0000 |
| commit | 57f13d5905a1fbdc89b53d68b2bdc6b753b9e8d5 (patch) | |
| tree | a982eecfcb9cde7c8326034f7af4a333a2ab66b8 /src/backends/reference/test/RefLayerTests.cpp | |
| parent | 34757810f8b734f5f59485a542b56934ad4cc5f0 (diff) | |
| download | armnn-57f13d5905a1fbdc89b53d68b2bdc6b753b9e8d5.tar.gz | |
IVGCVSW-3334 Refactor BatchToSpace tests to be generic
* Generify and reformat test BatchToSpace tests
* Add missing RefCreateWorkload test
Change-Id: I08af018c07ee41df5b9d1e578d99bc03f38090ac
Signed-off-by: Francis Murtagh <francis.murtagh@arm.com>
Diffstat (limited to 'src/backends/reference/test/RefLayerTests.cpp')
| -rw-r--r-- | src/backends/reference/test/RefLayerTests.cpp | 52 |
1 files changed, 34 insertions, 18 deletions
diff --git a/src/backends/reference/test/RefLayerTests.cpp b/src/backends/reference/test/RefLayerTests.cpp index 9cb8d13adc..4cb261f07d 100644 --- a/src/backends/reference/test/RefLayerTests.cpp +++ b/src/backends/reference/test/RefLayerTests.cpp @@ -811,24 +811,40 @@ ARMNN_AUTO_TEST_CASE(SpaceToBatchNdMultiChannelsNHWCUint16, SpaceToBatchNdMultiC ARMNN_AUTO_TEST_CASE(SpaceToBatchNdMultiBlockNHWCUint16, SpaceToBatchNdMultiBlockNHWCUint16Test) ARMNN_AUTO_TEST_CASE(SpaceToBatchNdPaddingNHWCUint16, SpaceToBatchNdPaddingNHWCUint16Test) -ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcFloat321, BatchToSpaceNdNhwcFloat32Test1) -ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcFloat322, BatchToSpaceNdNhwcFloat32Test2) -ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcFloat323, BatchToSpaceNdNhwcFloat32Test3) -ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcFloat324, BatchToSpaceNdNhwcFloat32Test4) - -ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwFloat321, BatchToSpaceNdNchwFloat32Test1) -ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwFloat322, BatchToSpaceNdNchwFloat32Test2) -ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwFloat323, BatchToSpaceNdNchwFloat32Test3) - -ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcUint1, BatchToSpaceNdNhwcUintTest1) -ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcUint2, BatchToSpaceNdNhwcUintTest2) -ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcUint3, BatchToSpaceNdNhwcUintTest3) - -ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwUint1, BatchToSpaceNdNchwUintTest1) -ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwUint2, BatchToSpaceNdNchwUintTest2) -ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwUint3, BatchToSpaceNdNchwUintTest3) -ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwUint4, BatchToSpaceNdNchwUintTest4) - +// BatchToSpace +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcFloat1, BatchToSpaceNdNhwcTest1<armnn::DataType::Float32>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcFloat2, BatchToSpaceNdNhwcTest2<armnn::DataType::Float32>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcFloat3, BatchToSpaceNdNhwcTest3<armnn::DataType::Float32>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcFloat4, BatchToSpaceNdNhwcTest4<armnn::DataType::Float32>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcFloat5, BatchToSpaceNdNhwcTest5<armnn::DataType::Float32>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcFloat6, BatchToSpaceNdNhwcTest6<armnn::DataType::Float32>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcFloat7, BatchToSpaceNdNhwcTest7<armnn::DataType::Float32>) + +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcUint1, BatchToSpaceNdNhwcTest1<armnn::DataType::QuantisedAsymm8>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcUint2, BatchToSpaceNdNhwcTest2<armnn::DataType::QuantisedAsymm8>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcUint3, BatchToSpaceNdNhwcTest3<armnn::DataType::QuantisedAsymm8>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcUint4, BatchToSpaceNdNhwcTest4<armnn::DataType::QuantisedAsymm8>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcUint5, BatchToSpaceNdNhwcTest5<armnn::DataType::QuantisedAsymm8>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcUint6, BatchToSpaceNdNhwcTest6<armnn::DataType::QuantisedAsymm8>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNhwcUint7, BatchToSpaceNdNhwcTest7<armnn::DataType::QuantisedAsymm8>) + +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwFloat1, BatchToSpaceNdNchwTest1<armnn::DataType::Float32>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwFloat2, BatchToSpaceNdNchwTest2<armnn::DataType::Float32>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwFloat3, BatchToSpaceNdNchwTest3<armnn::DataType::Float32>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwFloat4, BatchToSpaceNdNchwTest4<armnn::DataType::Float32>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwFloat5, BatchToSpaceNdNchwTest5<armnn::DataType::Float32>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwFloat6, BatchToSpaceNdNchwTest6<armnn::DataType::Float32>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwFloat7, BatchToSpaceNdNchwTest7<armnn::DataType::Float32>) + +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwUint1, BatchToSpaceNdNchwTest1<armnn::DataType::QuantisedAsymm8>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwUint2, BatchToSpaceNdNchwTest2<armnn::DataType::QuantisedAsymm8>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwUint3, BatchToSpaceNdNchwTest3<armnn::DataType::QuantisedAsymm8>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwUint4, BatchToSpaceNdNchwTest4<armnn::DataType::QuantisedAsymm8>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwUint5, BatchToSpaceNdNchwTest5<armnn::DataType::QuantisedAsymm8>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwUint6, BatchToSpaceNdNchwTest6<armnn::DataType::QuantisedAsymm8>) +ARMNN_AUTO_TEST_CASE(BatchToSpaceNdNchwUint7, BatchToSpaceNdNchwTest7<armnn::DataType::QuantisedAsymm8>) + +// SpaceToDepth ARMNN_AUTO_TEST_CASE(SpaceToDepthNCHWAsymmQ8, SpaceToDepthNCHWAsymmQ8Test) ARMNN_AUTO_TEST_CASE(SpaceToDepthNHWCAsymmQ8, SpaceToDepthNHWCAsymmQ8Test) |