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author | James Conroy <james.conroy@arm.com> | 2020-11-13 10:18:51 +0000 |
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committer | Teresa Charlin <teresa.charlinreyes@arm.com> | 2020-11-18 20:26:13 +0000 |
commit | 177df1e4483184e526f61a6bd1c00f9b33577571 (patch) | |
tree | 66c98f7bb80af2f7f86319c18c0ee0f4291cf1f0 /src/backends/neon/workloads/NeonLogicalOrWorkload.cpp | |
parent | 0c95f4cd319874ffa4aba3a378e0e3346f688fdc (diff) | |
download | armnn-177df1e4483184e526f61a6bd1c00f9b33577571.tar.gz |
IVGCVSW-5093 Add NEON Logical workload
* Add NEON Logical workloads for NOT,
AND and OR.
* Enable Layer and IsSupported tests on NEON.
Signed-off-by: James Conroy <james.conroy@arm.com>
Change-Id: Ibca59530457a664ca3d77751825642f8daf52fab
Diffstat (limited to 'src/backends/neon/workloads/NeonLogicalOrWorkload.cpp')
-rw-r--r-- | src/backends/neon/workloads/NeonLogicalOrWorkload.cpp | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/src/backends/neon/workloads/NeonLogicalOrWorkload.cpp b/src/backends/neon/workloads/NeonLogicalOrWorkload.cpp new file mode 100644 index 0000000000..c3f21e149d --- /dev/null +++ b/src/backends/neon/workloads/NeonLogicalOrWorkload.cpp @@ -0,0 +1,51 @@ +// +// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "NeonLogicalOrWorkload.hpp" + +#include "NeonWorkloadUtils.hpp" + +#include <aclCommon/ArmComputeTensorHandle.hpp> +#include <aclCommon/ArmComputeTensorUtils.hpp> + +#include <armnn/utility/PolymorphicDowncast.hpp> + +namespace armnn +{ + +arm_compute::Status NeonLogicalOrWorkloadValidate(const TensorInfo& input0, + const TensorInfo& input1, + const TensorInfo& output) +{ + const arm_compute::TensorInfo aclInputInfo0 = BuildArmComputeTensorInfo(input0); + const arm_compute::TensorInfo aclInputInfo1 = BuildArmComputeTensorInfo(input1); + const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output); + + const arm_compute::Status aclStatus = arm_compute::NELogicalOr::validate(&aclInputInfo0, + &aclInputInfo1, + &aclOutputInfo); + return aclStatus; +} + +NeonLogicalOrWorkload::NeonLogicalOrWorkload(const LogicalBinaryQueueDescriptor& descriptor, + const WorkloadInfo& info) + : BaseWorkload<LogicalBinaryQueueDescriptor>(descriptor, info) +{ + m_Data.ValidateInputsOutputs("NeonLogicalOrWorkload", 2, 1); + + arm_compute::ITensor& input0 = PolymorphicDowncast<IAclTensorHandle*>(m_Data.m_Inputs[0])->GetTensor(); + arm_compute::ITensor& input1 = PolymorphicDowncast<IAclTensorHandle*>(m_Data.m_Inputs[1])->GetTensor(); + arm_compute::ITensor& output = PolymorphicDowncast<IAclTensorHandle*>(m_Data.m_Outputs[0])->GetTensor(); + + m_LogicalOrLayer.configure(&input0, &input1, &output); +} + +void NeonLogicalOrWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_NEON("NeonLogicalOrWorkload_Execute"); + m_LogicalOrLayer.run(); +} + +} // namespace armnn |