diff options
author | James Conroy <james.conroy@arm.com> | 2020-11-18 14:20:53 +0000 |
---|---|---|
committer | Francis Murtagh <francis.murtagh@arm.com> | 2020-11-18 21:38:19 +0000 |
commit | fe3ec944c2573c54585f40b58ae6a36f8c19b009 (patch) | |
tree | 7abe3d7255c2ea595ca6ebd60dd18bcf242000fc /src/backends/cl/workloads | |
parent | b8307527963240e1594a12636462fd0577b3c6f4 (diff) | |
download | armnn-fe3ec944c2573c54585f40b58ae6a36f8c19b009.tar.gz |
IVGCVSW-5092 Add CL Logical workload
* Add CL Logical workloads for NOT,
AND and OR.
* Enable Layer and IsSupported tests on CL.
Signed-off-by: James Conroy <james.conroy@arm.com>
Change-Id: I8b7227b2487fdbbb55a4baf6e61f290313947de1
Diffstat (limited to 'src/backends/cl/workloads')
-rw-r--r-- | src/backends/cl/workloads/CMakeLists.txt | 6 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClLogicalAndWorkload.cpp | 53 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClLogicalAndWorkload.hpp | 30 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClLogicalNotWorkload.cpp | 49 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClLogicalNotWorkload.hpp | 28 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClLogicalOrWorkload.cpp | 53 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClLogicalOrWorkload.hpp | 30 | ||||
-rw-r--r-- | src/backends/cl/workloads/ClWorkloads.hpp | 3 |
8 files changed, 252 insertions, 0 deletions
diff --git a/src/backends/cl/workloads/CMakeLists.txt b/src/backends/cl/workloads/CMakeLists.txt index 24c09ad429..6118d9bbe1 100644 --- a/src/backends/cl/workloads/CMakeLists.txt +++ b/src/backends/cl/workloads/CMakeLists.txt @@ -50,6 +50,12 @@ list(APPEND armnnClBackendWorkloads_sources ClInstanceNormalizationWorkload.hpp ClL2NormalizationFloatWorkload.cpp ClL2NormalizationFloatWorkload.hpp + ClLogicalAndWorkload.cpp + ClLogicalAndWorkload.hpp + ClLogicalNotWorkload.cpp + ClLogicalNotWorkload.hpp + ClLogicalOrWorkload.cpp + ClLogicalOrWorkload.hpp ClLogSoftmaxWorkload.cpp ClLogSoftmaxWorkload.hpp ClLstmFloatWorkload.cpp diff --git a/src/backends/cl/workloads/ClLogicalAndWorkload.cpp b/src/backends/cl/workloads/ClLogicalAndWorkload.cpp new file mode 100644 index 0000000000..9418d73c23 --- /dev/null +++ b/src/backends/cl/workloads/ClLogicalAndWorkload.cpp @@ -0,0 +1,53 @@ +// +// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "ClLogicalAndWorkload.hpp" + +#include "ClWorkloadUtils.hpp" + +#include <armnn/utility/PolymorphicDowncast.hpp> + +#include <aclCommon/ArmComputeTensorUtils.hpp> + +#include <cl/ClTensorHandle.hpp> + +namespace armnn +{ +using namespace armcomputetensorutils; + +arm_compute::Status ClLogicalAndWorkloadValidate(const TensorInfo& input0, + const TensorInfo& input1, + const TensorInfo& output) +{ + const arm_compute::TensorInfo aclInputInfo0 = BuildArmComputeTensorInfo(input0); + const arm_compute::TensorInfo aclInputInfo1 = BuildArmComputeTensorInfo(input1); + const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output); + + const arm_compute::Status aclStatus = arm_compute::CLLogicalAnd::validate(&aclInputInfo0, + &aclInputInfo1, + &aclOutputInfo); + return aclStatus; +} + +ClLogicalAndWorkload::ClLogicalAndWorkload(const LogicalBinaryQueueDescriptor& descriptor, + const WorkloadInfo& info) + : BaseWorkload<LogicalBinaryQueueDescriptor>(descriptor, info) +{ + m_Data.ValidateInputsOutputs("ClLogicalAndWorkload", 2, 1); + + arm_compute::ICLTensor& input0 = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor(); + arm_compute::ICLTensor& input1 = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[1])->GetTensor(); + arm_compute::ICLTensor& output = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor(); + + m_LogicalAndLayer.configure(&input0, &input1, &output); +} + +void ClLogicalAndWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_CL("ClLogicalAndWorkload_Execute"); + m_LogicalAndLayer.run(); +} + +} // namespace armnn diff --git a/src/backends/cl/workloads/ClLogicalAndWorkload.hpp b/src/backends/cl/workloads/ClLogicalAndWorkload.hpp new file mode 100644 index 0000000000..3bf6afe9d4 --- /dev/null +++ b/src/backends/cl/workloads/ClLogicalAndWorkload.hpp @@ -0,0 +1,30 @@ +// +// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include <backendsCommon/Workload.hpp> + +#include <arm_compute/core/Error.h> +#include <arm_compute/runtime/CL/functions/CLLogicalAnd.h> + +namespace armnn +{ + +arm_compute::Status ClLogicalAndWorkloadValidate(const TensorInfo& input0, + const TensorInfo& input1, + const TensorInfo& output); + +class ClLogicalAndWorkload : public BaseWorkload<LogicalBinaryQueueDescriptor> +{ +public: + ClLogicalAndWorkload(const LogicalBinaryQueueDescriptor& descriptor, const WorkloadInfo& info); + virtual void Execute() const override; + +private: + mutable arm_compute::CLLogicalAnd m_LogicalAndLayer; +}; + +} //namespace armnn diff --git a/src/backends/cl/workloads/ClLogicalNotWorkload.cpp b/src/backends/cl/workloads/ClLogicalNotWorkload.cpp new file mode 100644 index 0000000000..eb90cafd1c --- /dev/null +++ b/src/backends/cl/workloads/ClLogicalNotWorkload.cpp @@ -0,0 +1,49 @@ +// +// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "ClLogicalNotWorkload.hpp" + +#include "ClWorkloadUtils.hpp" + +#include <armnn/utility/PolymorphicDowncast.hpp> + +#include <aclCommon/ArmComputeTensorUtils.hpp> + +#include <cl/ClTensorHandle.hpp> + +namespace armnn +{ +using namespace armcomputetensorutils; + +arm_compute::Status ClLogicalNotWorkloadValidate(const TensorInfo& input, + const TensorInfo& output) +{ + const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input); + const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output); + + const arm_compute::Status aclStatus = arm_compute::CLLogicalNot::validate(&aclInputInfo, + &aclOutputInfo); + return aclStatus; +} + +ClLogicalNotWorkload::ClLogicalNotWorkload(const ElementwiseUnaryQueueDescriptor& descriptor, + const WorkloadInfo& info) + : BaseWorkload<ElementwiseUnaryQueueDescriptor>(descriptor, info) +{ + m_Data.ValidateInputsOutputs("ClLogicalNotWorkload", 1, 1); + + arm_compute::ICLTensor& input = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor(); + arm_compute::ICLTensor& output = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor(); + + m_LogicalNotLayer.configure(&input, &output); +} + +void ClLogicalNotWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_CL("ClLogicalNotWorkload_Execute"); + m_LogicalNotLayer.run(); +} + +} // namespace armnn diff --git a/src/backends/cl/workloads/ClLogicalNotWorkload.hpp b/src/backends/cl/workloads/ClLogicalNotWorkload.hpp new file mode 100644 index 0000000000..f1225c7ba7 --- /dev/null +++ b/src/backends/cl/workloads/ClLogicalNotWorkload.hpp @@ -0,0 +1,28 @@ +// +// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include <backendsCommon/Workload.hpp> + +#include <arm_compute/core/Error.h> +#include <arm_compute/runtime/CL/functions/CLLogicalNot.h> + +namespace armnn +{ + +arm_compute::Status ClLogicalNotWorkloadValidate(const TensorInfo& input, const TensorInfo& output); + +class ClLogicalNotWorkload : public BaseWorkload<ElementwiseUnaryQueueDescriptor> +{ +public: + ClLogicalNotWorkload(const ElementwiseUnaryQueueDescriptor& descriptor, const WorkloadInfo& info); + virtual void Execute() const override; + +private: + mutable arm_compute::CLLogicalNot m_LogicalNotLayer; +}; + +} //namespace armnn diff --git a/src/backends/cl/workloads/ClLogicalOrWorkload.cpp b/src/backends/cl/workloads/ClLogicalOrWorkload.cpp new file mode 100644 index 0000000000..e9895bfc39 --- /dev/null +++ b/src/backends/cl/workloads/ClLogicalOrWorkload.cpp @@ -0,0 +1,53 @@ +// +// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "ClLogicalOrWorkload.hpp" + +#include "ClWorkloadUtils.hpp" + +#include <armnn/utility/PolymorphicDowncast.hpp> + +#include <aclCommon/ArmComputeTensorUtils.hpp> + +#include <cl/ClTensorHandle.hpp> + +namespace armnn +{ +using namespace armcomputetensorutils; + +arm_compute::Status ClLogicalOrWorkloadValidate(const TensorInfo& input0, + const TensorInfo& input1, + const TensorInfo& output) +{ + const arm_compute::TensorInfo aclInputInfo0 = BuildArmComputeTensorInfo(input0); + const arm_compute::TensorInfo aclInputInfo1 = BuildArmComputeTensorInfo(input1); + const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output); + + const arm_compute::Status aclStatus = arm_compute::CLLogicalOr::validate(&aclInputInfo0, + &aclInputInfo1, + &aclOutputInfo); + return aclStatus; +} + +ClLogicalOrWorkload::ClLogicalOrWorkload(const LogicalBinaryQueueDescriptor& descriptor, + const WorkloadInfo& info) + : BaseWorkload<LogicalBinaryQueueDescriptor>(descriptor, info) +{ + m_Data.ValidateInputsOutputs("ClLogicalOrWorkload", 2, 1); + + arm_compute::ICLTensor& input0 = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor(); + arm_compute::ICLTensor& input1 = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[1])->GetTensor(); + arm_compute::ICLTensor& output = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor(); + + m_LogicalOrLayer.configure(&input0, &input1, &output); +} + +void ClLogicalOrWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_CL("ClLogicalOrWorkload_Execute"); + m_LogicalOrLayer.run(); +} + +} // namespace armnn diff --git a/src/backends/cl/workloads/ClLogicalOrWorkload.hpp b/src/backends/cl/workloads/ClLogicalOrWorkload.hpp new file mode 100644 index 0000000000..8faabde90a --- /dev/null +++ b/src/backends/cl/workloads/ClLogicalOrWorkload.hpp @@ -0,0 +1,30 @@ +// +// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#pragma once + +#include <backendsCommon/Workload.hpp> + +#include <arm_compute/core/Error.h> +#include <arm_compute/runtime/CL/functions/CLLogicalOr.h> + +namespace armnn +{ + +arm_compute::Status ClLogicalOrWorkloadValidate(const TensorInfo& input0, + const TensorInfo& input1, + const TensorInfo& output); + +class ClLogicalOrWorkload : public BaseWorkload<LogicalBinaryQueueDescriptor> +{ +public: + ClLogicalOrWorkload(const LogicalBinaryQueueDescriptor& descriptor, const WorkloadInfo& info); + virtual void Execute() const override; + +private: + mutable arm_compute::CLLogicalOr m_LogicalOrLayer; +}; + +} //namespace armnn diff --git a/src/backends/cl/workloads/ClWorkloads.hpp b/src/backends/cl/workloads/ClWorkloads.hpp index b48e5a62f6..efcccb35c3 100644 --- a/src/backends/cl/workloads/ClWorkloads.hpp +++ b/src/backends/cl/workloads/ClWorkloads.hpp @@ -24,6 +24,9 @@ #include "ClGatherWorkload.hpp" #include "ClInstanceNormalizationWorkload.hpp" #include "ClL2NormalizationFloatWorkload.hpp" +#include "ClLogicalAndWorkload.hpp" +#include "ClLogicalNotWorkload.hpp" +#include "ClLogicalOrWorkload.hpp" #include "ClLogSoftmaxWorkload.hpp" #include "ClLstmFloatWorkload.hpp" #include "ClConcatWorkload.hpp" |