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author | James Conroy <james.conroy@arm.com> | 2020-11-18 14:20:53 +0000 |
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committer | Francis Murtagh <francis.murtagh@arm.com> | 2020-11-18 21:38:19 +0000 |
commit | fe3ec944c2573c54585f40b58ae6a36f8c19b009 (patch) | |
tree | 7abe3d7255c2ea595ca6ebd60dd18bcf242000fc /src/backends/cl/workloads/ClLogicalNotWorkload.cpp | |
parent | b8307527963240e1594a12636462fd0577b3c6f4 (diff) | |
download | armnn-fe3ec944c2573c54585f40b58ae6a36f8c19b009.tar.gz |
IVGCVSW-5092 Add CL Logical workload
* Add CL Logical workloads for NOT,
AND and OR.
* Enable Layer and IsSupported tests on CL.
Signed-off-by: James Conroy <james.conroy@arm.com>
Change-Id: I8b7227b2487fdbbb55a4baf6e61f290313947de1
Diffstat (limited to 'src/backends/cl/workloads/ClLogicalNotWorkload.cpp')
-rw-r--r-- | src/backends/cl/workloads/ClLogicalNotWorkload.cpp | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/src/backends/cl/workloads/ClLogicalNotWorkload.cpp b/src/backends/cl/workloads/ClLogicalNotWorkload.cpp new file mode 100644 index 0000000000..eb90cafd1c --- /dev/null +++ b/src/backends/cl/workloads/ClLogicalNotWorkload.cpp @@ -0,0 +1,49 @@ +// +// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "ClLogicalNotWorkload.hpp" + +#include "ClWorkloadUtils.hpp" + +#include <armnn/utility/PolymorphicDowncast.hpp> + +#include <aclCommon/ArmComputeTensorUtils.hpp> + +#include <cl/ClTensorHandle.hpp> + +namespace armnn +{ +using namespace armcomputetensorutils; + +arm_compute::Status ClLogicalNotWorkloadValidate(const TensorInfo& input, + const TensorInfo& output) +{ + const arm_compute::TensorInfo aclInputInfo = BuildArmComputeTensorInfo(input); + const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output); + + const arm_compute::Status aclStatus = arm_compute::CLLogicalNot::validate(&aclInputInfo, + &aclOutputInfo); + return aclStatus; +} + +ClLogicalNotWorkload::ClLogicalNotWorkload(const ElementwiseUnaryQueueDescriptor& descriptor, + const WorkloadInfo& info) + : BaseWorkload<ElementwiseUnaryQueueDescriptor>(descriptor, info) +{ + m_Data.ValidateInputsOutputs("ClLogicalNotWorkload", 1, 1); + + arm_compute::ICLTensor& input = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor(); + arm_compute::ICLTensor& output = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor(); + + m_LogicalNotLayer.configure(&input, &output); +} + +void ClLogicalNotWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_CL("ClLogicalNotWorkload_Execute"); + m_LogicalNotLayer.run(); +} + +} // namespace armnn |