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author | James Conroy <james.conroy@arm.com> | 2020-11-18 14:20:53 +0000 |
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committer | Francis Murtagh <francis.murtagh@arm.com> | 2020-11-18 21:38:19 +0000 |
commit | fe3ec944c2573c54585f40b58ae6a36f8c19b009 (patch) | |
tree | 7abe3d7255c2ea595ca6ebd60dd18bcf242000fc /src/backends/cl/workloads/ClLogicalAndWorkload.cpp | |
parent | b8307527963240e1594a12636462fd0577b3c6f4 (diff) | |
download | armnn-fe3ec944c2573c54585f40b58ae6a36f8c19b009.tar.gz |
IVGCVSW-5092 Add CL Logical workload
* Add CL Logical workloads for NOT,
AND and OR.
* Enable Layer and IsSupported tests on CL.
Signed-off-by: James Conroy <james.conroy@arm.com>
Change-Id: I8b7227b2487fdbbb55a4baf6e61f290313947de1
Diffstat (limited to 'src/backends/cl/workloads/ClLogicalAndWorkload.cpp')
-rw-r--r-- | src/backends/cl/workloads/ClLogicalAndWorkload.cpp | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/src/backends/cl/workloads/ClLogicalAndWorkload.cpp b/src/backends/cl/workloads/ClLogicalAndWorkload.cpp new file mode 100644 index 0000000000..9418d73c23 --- /dev/null +++ b/src/backends/cl/workloads/ClLogicalAndWorkload.cpp @@ -0,0 +1,53 @@ +// +// Copyright © 2020 Arm Ltd and Contributors. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "ClLogicalAndWorkload.hpp" + +#include "ClWorkloadUtils.hpp" + +#include <armnn/utility/PolymorphicDowncast.hpp> + +#include <aclCommon/ArmComputeTensorUtils.hpp> + +#include <cl/ClTensorHandle.hpp> + +namespace armnn +{ +using namespace armcomputetensorutils; + +arm_compute::Status ClLogicalAndWorkloadValidate(const TensorInfo& input0, + const TensorInfo& input1, + const TensorInfo& output) +{ + const arm_compute::TensorInfo aclInputInfo0 = BuildArmComputeTensorInfo(input0); + const arm_compute::TensorInfo aclInputInfo1 = BuildArmComputeTensorInfo(input1); + const arm_compute::TensorInfo aclOutputInfo = BuildArmComputeTensorInfo(output); + + const arm_compute::Status aclStatus = arm_compute::CLLogicalAnd::validate(&aclInputInfo0, + &aclInputInfo1, + &aclOutputInfo); + return aclStatus; +} + +ClLogicalAndWorkload::ClLogicalAndWorkload(const LogicalBinaryQueueDescriptor& descriptor, + const WorkloadInfo& info) + : BaseWorkload<LogicalBinaryQueueDescriptor>(descriptor, info) +{ + m_Data.ValidateInputsOutputs("ClLogicalAndWorkload", 2, 1); + + arm_compute::ICLTensor& input0 = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor(); + arm_compute::ICLTensor& input1 = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Inputs[1])->GetTensor(); + arm_compute::ICLTensor& output = PolymorphicDowncast<ClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor(); + + m_LogicalAndLayer.configure(&input0, &input1, &output); +} + +void ClLogicalAndWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_CL("ClLogicalAndWorkload_Execute"); + m_LogicalAndLayer.run(); +} + +} // namespace armnn |