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author | Teresa Charlin <teresa.charlinreyes@arm.com> | 2021-04-21 12:56:45 +0100 |
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committer | TeresaARM <teresa.charlinreyes@arm.com> | 2021-04-21 16:26:15 +0000 |
commit | e11e63d749b0909f13f9a39c8d34ef5523255170 (patch) | |
tree | 7a44acf59176dabd663dd36b815875b390918b68 /src/backends/cl/workloads/ClDivisionWorkload.cpp | |
parent | fe95d7203ba7a6ac31e0656190ba56de6fcf4735 (diff) | |
download | armnn-e11e63d749b0909f13f9a39c8d34ef5523255170.tar.gz |
IVGCVSW-5909 Fix CTS failure in GpuAcc DIV int32
* CLWorkload was only supporting float
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: Ic57a490f03a055c158edc19e831b153a44e25166
Diffstat (limited to 'src/backends/cl/workloads/ClDivisionWorkload.cpp')
-rw-r--r-- | src/backends/cl/workloads/ClDivisionWorkload.cpp | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/src/backends/cl/workloads/ClDivisionWorkload.cpp b/src/backends/cl/workloads/ClDivisionWorkload.cpp new file mode 100644 index 0000000000..be5f3b8225 --- /dev/null +++ b/src/backends/cl/workloads/ClDivisionWorkload.cpp @@ -0,0 +1,56 @@ +// +// Copyright © 2017 Arm Ltd. All rights reserved. +// SPDX-License-Identifier: MIT +// + +#include "ClDivisionWorkload.hpp" + +#include <aclCommon/ArmComputeUtils.hpp> +#include <backendsCommon/CpuTensorHandle.hpp> + +#include <cl/ClTensorHandle.hpp> + +#include "ClWorkloadUtils.hpp" + +namespace armnn +{ + +arm_compute::Status ClDivisionWorkloadValidate(const TensorInfo& input0, + const TensorInfo& input1, + const TensorInfo& output, + const ActivationDescriptor* activationDescriptor) +{ + const arm_compute::TensorInfo aclInput1 = armcomputetensorutils::BuildArmComputeTensorInfo(input0); + const arm_compute::TensorInfo aclInput2 = armcomputetensorutils::BuildArmComputeTensorInfo(input1); + const arm_compute::TensorInfo aclOutput = armcomputetensorutils::BuildArmComputeTensorInfo(output); + + const arm_compute::ActivationLayerInfo activationInfo = ConvertActivationDescriptorToAclActivationLayerInfo( + activationDescriptor); + + return arm_compute::CLArithmeticDivision::validate(&aclInput1, &aclInput2, &aclOutput, activationInfo); +} + + +ClDivisionWorkload::ClDivisionWorkload(const DivisionQueueDescriptor& descriptor, + const WorkloadInfo& info, + const arm_compute::CLCompileContext& clCompileContext) + : BaseWorkload<DivisionQueueDescriptor>(descriptor, info) +{ + m_Data.ValidateInputsOutputs("ClDivisionWorkload", 2, 1); + + arm_compute::ICLTensor& input0 = static_cast<IClTensorHandle*>(m_Data.m_Inputs[0])->GetTensor(); + arm_compute::ICLTensor& input1 = static_cast<IClTensorHandle*>(m_Data.m_Inputs[1])->GetTensor(); + arm_compute::ICLTensor& output = static_cast<IClTensorHandle*>(m_Data.m_Outputs[0])->GetTensor(); + + const arm_compute::ActivationLayerInfo activationInfo = ConvertAdditionalInfoToAclActivationLayerInfo(descriptor); + + m_ArithmeticDivision.configure(clCompileContext, &input0, &input1, &output, activationInfo); +} + +void ClDivisionWorkload::Execute() const +{ + ARMNN_SCOPED_PROFILING_EVENT_CL("ClDivisionWorkload_Execute"); + RunClFunction(m_ArithmeticDivision, CHECK_LOCATION()); +} + +} //namespace armnn |