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| author | Teresa Charlin <teresa.charlinreyes@arm.com> | 2021-10-22 17:15:00 +0100 |
|---|---|---|
| committer | TeresaARM <teresa.charlinreyes@arm.com> | 2021-10-27 09:32:11 +0000 |
| commit | ec5f7d13582d1e477dc3473223b503388092a352 (patch) | |
| tree | 37c4d6299f0726a853e28f6297d4eb222cda2c68 /src/backends/aclCommon/ArmComputeTensorUtils.hpp | |
| parent | e1fdd2866b0f403b5e80994890d62c2c038c16c9 (diff) | |
| download | armnn-ec5f7d13582d1e477dc3473223b503388092a352.tar.gz | |
IVGCVSW-6170 Add CpuAcc Conv3d Workload
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I3a5bfef5a0085d172fd3689e67f25af909ace2ee
Diffstat (limited to 'src/backends/aclCommon/ArmComputeTensorUtils.hpp')
| -rw-r--r-- | src/backends/aclCommon/ArmComputeTensorUtils.hpp | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/backends/aclCommon/ArmComputeTensorUtils.hpp b/src/backends/aclCommon/ArmComputeTensorUtils.hpp index 011f44dc69..ad5d4614fe 100644 --- a/src/backends/aclCommon/ArmComputeTensorUtils.hpp +++ b/src/backends/aclCommon/ArmComputeTensorUtils.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2017 Arm Ltd. All rights reserved. +// Copyright © 2017 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once @@ -12,7 +12,6 @@ #include <arm_compute/core/ITensor.h> #include <arm_compute/core/TensorInfo.h> #include <arm_compute/core/Types.h> -#include <arm_compute/core/Size2D.h> #include <Half.hpp> |