aboutsummaryrefslogtreecommitdiff
path: root/src/armnn/backends/ClWorkloads/ClWorkloadUtils.hpp
diff options
context:
space:
mode:
authorMatthew Bentham <Matthew.Bentham@arm.com>2018-09-20 15:35:30 +0100
committerMatthew Bentham <matthew.bentham@arm.com>2018-10-10 16:16:56 +0100
commit14e4669b88aba8816211e2f5a5b7e8d774ce2ad4 (patch)
treeb55a87697ce4f8353c8405aee211bcf6edb6d2f6 /src/armnn/backends/ClWorkloads/ClWorkloadUtils.hpp
parentab8cdc13443408d727fd38be42315cf942251940 (diff)
downloadarmnn-14e4669b88aba8816211e2f5a5b7e8d774ce2ad4.tar.gz
IVGCVSW-949 Refactor - clean up includes of ClWorkloadUtils.hpp
Move ClWorkloadUtils.hpp into ClWorkloads and reduce the number of places that include it Change-Id: Iac661be34c185d6208ca75509155b049c24293ca
Diffstat (limited to 'src/armnn/backends/ClWorkloads/ClWorkloadUtils.hpp')
-rw-r--r--src/armnn/backends/ClWorkloads/ClWorkloadUtils.hpp67
1 files changed, 67 insertions, 0 deletions
diff --git a/src/armnn/backends/ClWorkloads/ClWorkloadUtils.hpp b/src/armnn/backends/ClWorkloads/ClWorkloadUtils.hpp
new file mode 100644
index 0000000000..a42e48c97d
--- /dev/null
+++ b/src/armnn/backends/ClWorkloads/ClWorkloadUtils.hpp
@@ -0,0 +1,67 @@
+//
+// Copyright © 2017 Arm Ltd. All rights reserved.
+// SPDX-License-Identifier: MIT
+//
+#pragma once
+
+#include "OpenClTimer.hpp"
+#include "backends/Workload.hpp"
+#include "backends/ArmComputeTensorUtils.hpp"
+#include "backends/CpuTensorHandle.hpp"
+
+#include <arm_compute/core/CL/OpenCL.h>
+#include <arm_compute/runtime/CL/CLFunctions.h>
+#include <arm_compute/runtime/SubTensor.h>
+
+#include <Half.hpp>
+
+#define ARMNN_SCOPED_PROFILING_EVENT_CL(name) \
+ ARMNN_SCOPED_PROFILING_EVENT_WITH_INSTRUMENTS(armnn::Compute::GpuAcc, \
+ name, \
+ armnn::OpenClTimer(), \
+ armnn::WallClockTimer())
+
+namespace armnn
+{
+
+template <typename T>
+void CopyArmComputeClTensorData(const T* srcData, arm_compute::CLTensor& dstTensor)
+{
+ {
+ ARMNN_SCOPED_PROFILING_EVENT_CL("MapClTensorForWriting");
+ dstTensor.map(true);
+ }
+
+ {
+ ARMNN_SCOPED_PROFILING_EVENT_CL("CopyToClTensor");
+ armcomputetensorutils::CopyArmComputeITensorData<T>(srcData, dstTensor);
+ }
+
+ dstTensor.unmap();
+}
+
+template <typename T>
+void InitialiseArmComputeClTensorData(arm_compute::CLTensor& clTensor, const T* data)
+{
+ armcomputetensorutils::InitialiseArmComputeTensorEmpty(clTensor);
+ CopyArmComputeClTensorData<T>(data, clTensor);
+}
+
+inline void InitializeArmComputeClTensorDataForFloatTypes(arm_compute::CLTensor& clTensor,
+ const ConstCpuTensorHandle *handle)
+{
+ BOOST_ASSERT(handle);
+ switch(handle->GetTensorInfo().GetDataType())
+ {
+ case DataType::Float16:
+ InitialiseArmComputeClTensorData(clTensor, handle->GetConstTensor<armnn::Half>());
+ break;
+ case DataType::Float32:
+ InitialiseArmComputeClTensorData(clTensor, handle->GetConstTensor<float>());
+ break;
+ default:
+ BOOST_ASSERT_MSG(false, "Unexpected floating point type.");
+ }
+};
+
+} //namespace armnn