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author | Teresa Charlin <teresa.charlinreyes@arm.com> | 2022-12-06 20:43:06 +0000 |
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committer | Teresa Charlin <teresa.charlinreyes@arm.com> | 2022-12-07 15:40:28 +0000 |
commit | 6bc85258b0a87cde2e1e644d930ea546b6c3a1cc (patch) | |
tree | 463e31a280a8a57b4d43acd9adb1e05de000b4c0 /include | |
parent | 4002a609b1e5a75d7527cd8b7cb05ed444d27caa (diff) | |
download | armnn-6bc85258b0a87cde2e1e644d930ea546b6c3a1cc.tar.gz |
IVGCVSW-6853 Rewrite BuildArmComputePermutationVector()
* Some pemutation vectors were not converted correctly.
* Add Transpose end to end test.
* Comments added with an example to clarify the differences betweeen
Transpose and Permute
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: I6c0954ca6ce00ef5f2a6f3625abe6f4fd27b5cdf
Diffstat (limited to 'include')
-rw-r--r-- | include/armnn/Descriptors.hpp | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/include/armnn/Descriptors.hpp b/include/armnn/Descriptors.hpp index 2540073090..1cc403cf99 100644 --- a/include/armnn/Descriptors.hpp +++ b/include/armnn/Descriptors.hpp @@ -1,5 +1,5 @@ // -// Copyright © 2022 Arm Ltd and Contributors. All rights reserved. +// Copyright © 2017,2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #pragma once @@ -142,7 +142,14 @@ struct PermuteDescriptor : BaseDescriptor } /// @brief Indicates how to translate tensor elements from a given source into the target destination, when - /// source and target potentially have different memory layouts e.g. {0U, 3U, 1U, 2U}. + /// source and target potentially have different memory layouts e.g. + /// Input Shape {1, 1, 4, 4} + /// Permutation Vector {0, 2, 3, 1} + /// Output Shape {1, 4, 1, 4} + /// dim "0" goes into index 0 ([ 1, X, X, X ]) + /// dim "1" goes into index 2 ([ 1, X, 1, X ]) + /// dim "2" goes into index 3 ([ 1, X, 1, 4 ]) + /// dim "3" goes into index 1 ([ 1, 4, 1, 4 ]) PermutationVector m_DimMappings; }; @@ -1443,7 +1450,14 @@ struct TransposeDescriptor : BaseDescriptor } /// @brief Indicates how to translate tensor elements from a given source into the target destination, when - /// source and target potentially have different memory layouts e.g. {0U, 3U, 1U, 2U}. + /// source and target potentially have different memory layouts e.g. + /// Input Shape {1, 1, 4, 4} + /// Permutation Vector {0, 2, 3, 1} + /// Output Shape {1, 4, 4, 1} + /// dim "0" of input goes into index 0 ([ 1, X, X, X]) + /// dim "2" of input goes into index 1 ([ 1, 4, X, X ]) + /// dim "3" of input goes into index 2 ([ 1, 4, 4, X ]) + /// dim "1" of input goes into index 3 ([ 1, 4, 4, 1 ]) PermutationVector m_DimMappings; }; |