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author | Teresa Charlin <teresa.charlinreyes@arm.com> | 2023-04-28 14:23:33 +0100 |
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committer | TeresaARM <teresa.charlinreyes@arm.com> | 2023-04-28 16:54:49 +0000 |
commit | 4236296b3715ca3cfe83142f2e170f8f48a7b18d (patch) | |
tree | a48932cc56a9fc7c99cacfce2904ccd5e75cf29a /delegate/opaque/src/Transpose.hpp | |
parent | 36d94ef824c516f27fad8f17a96e2123565e6f9f (diff) | |
download | armnn-4236296b3715ca3cfe83142f2e170f8f48a7b18d.tar.gz |
IVGCVSW-7611 IVGCVSW-7614 IVGCVSW-7615 IVGCVSW-7617 Softmax, SpaceToDepth, DepthToSpace and Tranpose for opaque delegate
Signed-off-by: Teresa Charlin <teresa.charlinreyes@arm.com>
Change-Id: Ie0c608f94a76956e9be75f555824cef865cab395
Diffstat (limited to 'delegate/opaque/src/Transpose.hpp')
-rw-r--r-- | delegate/opaque/src/Transpose.hpp | 110 |
1 files changed, 110 insertions, 0 deletions
diff --git a/delegate/opaque/src/Transpose.hpp b/delegate/opaque/src/Transpose.hpp index e16969768e..2627c42f1f 100644 --- a/delegate/opaque/src/Transpose.hpp +++ b/delegate/opaque/src/Transpose.hpp @@ -2,3 +2,113 @@ // Copyright © 2023 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // + +#pragma once + +#include <OpaqueDelegateUtils.hpp> + +namespace armnnOpaqueDelegate +{ + +TfLiteStatus VisitTransposeOperator(DelegateData& delegateData, + TfLiteOpaqueContext* tfLiteContext, + TfLiteOpaqueNode* tfLiteNode, + int nodeIndex, + int32_t tfliteTransposeOperatorCode) +{ + TF_LITE_ENSURE_STATUS(ValidateNumInputs(tfLiteContext, tfLiteNode, 2, nodeIndex)); + TF_LITE_ENSURE_STATUS(ValidateNumOutputs(tfLiteContext, tfLiteNode, 1, nodeIndex)); + + // Gather input indices and use to get input tensor. + const int* inputTensors; + int numInputs; + if (TfLiteOpaqueNodeInputs(tfLiteNode, &inputTensors, &numInputs) != kTfLiteOk) + { + TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( + tfLiteContext, + "TfLiteArmnnOpaqueDelegate: Unable to gather input tensor indices from node #%d: ", + nodeIndex); + return kTfLiteError; + } + const TfLiteOpaqueTensor* tfLiteInputTensor0 = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[0]); + if (!IsValid(tfLiteContext, tfLiteInputTensor0, tfliteTransposeOperatorCode, nodeIndex)) + { + return kTfLiteError; + } + const TfLiteOpaqueTensor* tfLiteInputTensor1 = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, inputTensors[1]); + if (!IsValid(tfLiteContext, tfLiteInputTensor1, tfliteTransposeOperatorCode, nodeIndex)) + { + return kTfLiteError; + } + + // Gather output indices and use to get output tensors. + const int* outputTensors; + int numOutputs; + if (TfLiteOpaqueNodeOutputs(tfLiteNode, &outputTensors, &numOutputs) != kTfLiteOk) + { + TF_LITE_OPAQUE_MAYBE_KERNEL_LOG( + tfLiteContext, + "TfLiteArmnnOpaqueDelegate: Unable to gather output tensor indices from node #%d: ", + nodeIndex); + return kTfLiteError; + } + + const TfLiteOpaqueTensor* tfLiteOutputTensor = TfLiteOpaqueContextGetOpaqueTensor(tfLiteContext, outputTensors[0]); + if (!IsValid(tfLiteContext, tfLiteOutputTensor, tfliteTransposeOperatorCode, nodeIndex)) + { + return kTfLiteError; + } + + const armnn::TensorInfo& inputTensorInfo0 = GetTensorInfoForTfLiteOpaqueTensor(tfLiteInputTensor0); + const armnn::TensorInfo& outputTensorInfo = GetTensorInfoForTfLiteOpaqueTensor(tfLiteOutputTensor, true); + + auto* permTensorDataPtr = static_cast<int32_t*>(TfLiteOpaqueTensorData(tfLiteInputTensor1)); + unsigned int numEl = TfLiteOpaqueTensorDim(tfLiteInputTensor1, 0); + + ARMNN_ASSERT( numEl <= static_cast<int>(armnn::MaxNumOfTensorDimensions) ); + // Ensure only single dimension to the permutation tensor + ARMNN_ASSERT( TfLiteOpaqueTensorNumDims(tfLiteInputTensor1) == 1 ); + + armnn::TransposeDescriptor descriptor(armnn::PermutationVector( + reinterpret_cast<const armnn::PermutationVector::ValueType *> (permTensorDataPtr), + static_cast<armnn::PermutationVector::SizeType>(numEl))); + + bool isSupported = false; + armnn::BackendId setBackend; + auto validateFunc = [&](const armnn::TensorInfo& outputTensorInfo, bool& isSupported) + { + FORWARD_LAYER_OPAQUE_SUPPORT_FUNC("TRANSPOSE", + tfLiteContext, + IsTransposeSupported, + delegateData.m_Backends, + isSupported, + setBackend, + inputTensorInfo0, + outputTensorInfo, + descriptor); + }; + + if (!delegateData.m_Network) + { + validateFunc(outputTensorInfo, isSupported); + return isSupported ? kTfLiteOk : kTfLiteError; + } + + armnn::IConnectableLayer* transposeLayer = delegateData.m_Network->AddTransposeLayer(descriptor); + transposeLayer->SetBackendId(setBackend); + ARMNN_ASSERT(transposeLayer != nullptr); + // Permutation vector given to descriptor object + ARMNN_ASSERT(transposeLayer->GetNumInputSlots() == 1); + + armnn::IOutputSlot& outputSlot = transposeLayer->GetOutputSlot(0); + outputSlot.SetTensorInfo(outputTensorInfo); + + // try to connect the Constant Inputs if there are any + if(ProcessInputs(transposeLayer,delegateData, tfLiteContext, tfLiteNode) != kTfLiteOk ) + { + return kTfLiteError; + } + + return Connect(transposeLayer, tfLiteContext, tfLiteNode, delegateData); +} +} // namespace armnnOpaqueDelegate |