From 3c673949b4ed3ab3129859b18439ed8fe87a6ad1 Mon Sep 17 00:00:00 2001
From: Mike Kelly <mike.kelly@arm.com>
Date: Thu, 25 Jul 2019 09:26:06 +0100
Subject: IVGCVSW-3521 CpuAcc V1.2 pad Failures

 * Fixed Pad and PadV2 failures and skips.
 * Templated ConvertPad to enable float16 tests to run.

Signed-off-by: Mike Kelly <mike.kelly@arm.com>
Change-Id: I50ded84fe44ea5d5949e877f383f32adff88680d
---
 Utils.cpp | 7 +++++++
 1 file changed, 7 insertions(+)

(limited to 'Utils.cpp')

diff --git a/Utils.cpp b/Utils.cpp
index d3d62a02..43b65ee3 100644
--- a/Utils.cpp
+++ b/Utils.cpp
@@ -7,6 +7,7 @@
 
 #include "Utils.hpp"
 
+#include <Half.hpp>
 #include <Permute.hpp>
 
 #include <cassert>
@@ -42,6 +43,9 @@ void SwizzleAndroidNn4dTensorToArmNn(const armnn::TensorInfo& tensor, const void
 
     switch(tensor.GetDataType())
     {
+    case armnn::DataType::Float16:
+        SwizzleAndroidNn4dTensorToArmNn<armnn::Half>(tensor.GetShape(), input, output, mappings);
+        break;
     case armnn::DataType::Float32:
         SwizzleAndroidNn4dTensorToArmNn<float>(tensor.GetShape(), input, output, mappings);
         break;
@@ -112,6 +116,9 @@ armnn::TensorInfo GetTensorInfoForOperand(const V1_2::Operand& operand)
         case V1_2::OperandType::TENSOR_FLOAT32:
             type = armnn::DataType::Float32;
             break;
+        case V1_2::OperandType::TENSOR_FLOAT16:
+            type = armnn::DataType::Float16;
+            break;
         case V1_2::OperandType::TENSOR_QUANT8_ASYMM:
             type = armnn::DataType::QuantisedAsymm8;
             break;
-- 
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