diff options
Diffstat (limited to 'test/1.1')
-rw-r--r-- | test/1.1/Convolution2D.cpp | 21 | ||||
-rw-r--r-- | test/1.1/Lstm.cpp | 64 | ||||
-rw-r--r-- | test/1.1/Mean.cpp | 207 | ||||
-rw-r--r-- | test/1.1/Transpose.cpp | 116 |
4 files changed, 293 insertions, 115 deletions
diff --git a/test/1.1/Convolution2D.cpp b/test/1.1/Convolution2D.cpp index 32d5018c..4601f760 100644 --- a/test/1.1/Convolution2D.cpp +++ b/test/1.1/Convolution2D.cpp @@ -1,19 +1,14 @@ // -// Copyright © 2017 Arm Ltd. All rights reserved. +// Copyright © 2017 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // -#include "../DriverTestHelpers.hpp" #include "../Convolution2D.hpp" -#include "../../1.1/HalPolicy.hpp" -#include <boost/test/unit_test.hpp> #include <log/log.h> #include <OperationsUtils.h> -BOOST_AUTO_TEST_SUITE(Convolution2DTests) - using namespace android::hardware; using namespace driverTestHelpers; using namespace armnn_driver; @@ -29,24 +24,28 @@ void SetModelFp16Flag(V1_1::Model& model, bool fp16Enabled) } // namespace driverTestHelpers -BOOST_AUTO_TEST_CASE(ConvValidPadding_Hal_1_1) + +DOCTEST_TEST_SUITE("Convolution2DTests_1.1") +{ + +DOCTEST_TEST_CASE("ConvValidPadding_Hal_1_1") { PaddingTestImpl<hal_1_1::HalPolicy>(android::nn::kPaddingValid); } -BOOST_AUTO_TEST_CASE(ConvSamePadding_Hal_1_1) +DOCTEST_TEST_CASE("ConvSamePadding_Hal_1_1") { PaddingTestImpl<hal_1_1::HalPolicy>(android::nn::kPaddingSame); } -BOOST_AUTO_TEST_CASE(ConvValidPaddingFp16Flag_Hal_1_1) +DOCTEST_TEST_CASE("ConvValidPaddingFp16Flag_Hal_1_1") { PaddingTestImpl<hal_1_1::HalPolicy>(android::nn::kPaddingValid, true); } -BOOST_AUTO_TEST_CASE(ConvSamePaddingFp16Flag_Hal_1_1) +DOCTEST_TEST_CASE("ConvSamePaddingFp16Flag_Hal_1_1") { PaddingTestImpl<hal_1_1::HalPolicy>(android::nn::kPaddingSame, true); } -BOOST_AUTO_TEST_SUITE_END() +} diff --git a/test/1.1/Lstm.cpp b/test/1.1/Lstm.cpp index 703597e5..cbdf6b14 100644 --- a/test/1.1/Lstm.cpp +++ b/test/1.1/Lstm.cpp @@ -1,34 +1,60 @@ // -// Copyright © 2017 Arm Ltd. All rights reserved. +// Copyright © 2017 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "../Lstm.hpp" -#include <boost/test/data/test_case.hpp> - -BOOST_AUTO_TEST_SUITE(LstmTests) - using namespace armnn_driver; -BOOST_DATA_TEST_CASE(LstmNoCifgNoPeepholeNoProjectionTest, COMPUTE_DEVICES) +DOCTEST_TEST_SUITE("LstmTests_1.1_CpuRef") { - LstmNoCifgNoPeepholeNoProjection<hal_1_1::HalPolicy>(sample); -} -BOOST_DATA_TEST_CASE(LstmCifgPeepholeNoProjectionTest, COMPUTE_DEVICES) -{ - LstmCifgPeepholeNoProjection<hal_1_1::HalPolicy>(sample); -} + DOCTEST_TEST_CASE("LstmNoCifgNoPeepholeNoProjectionTest_1.1_armnn::Compute::CpuRef") + { + LstmNoCifgNoPeepholeNoProjection<hal_1_1::HalPolicy>(armnn::Compute::CpuRef); + } + + DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionTest_1.1_CpuRef") + { + LstmCifgPeepholeNoProjection<hal_1_1::HalPolicy>(armnn::Compute::CpuRef); + } + + DOCTEST_TEST_CASE("LstmNoCifgPeepholeProjectionTest_1.1_CpuRef") + { + LstmNoCifgPeepholeProjection<hal_1_1::HalPolicy>(armnn::Compute::CpuRef); + } + + DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionBatch2Test_1.1_CpuRef") + { + LstmCifgPeepholeNoProjectionBatch2<hal_1_1::HalPolicy>(armnn::Compute::CpuRef); + } -BOOST_DATA_TEST_CASE(LstmNoCifgPeepholeProjectionTest, COMPUTE_DEVICES) -{ - LstmNoCifgPeepholeProjection<hal_1_1::HalPolicy>(sample); } -BOOST_DATA_TEST_CASE(LstmCifgPeepholeNoProjectionBatch2Test, COMPUTE_DEVICES) +#if defined(ARMCOMPUTECL_ENABLED) +DOCTEST_TEST_SUITE("LstmTests_1.1_GpuAcc") { - LstmCifgPeepholeNoProjectionBatch2<hal_1_1::HalPolicy>(sample); -} -BOOST_AUTO_TEST_SUITE_END() + DOCTEST_TEST_CASE("LstmNoCifgNoPeepholeNoProjectionTest_1.1_GpuAcc") + { + LstmNoCifgNoPeepholeNoProjection<hal_1_1::HalPolicy>(armnn::Compute::GpuAcc); + } + + DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionTest_1.1_GpuAcc") + { + LstmCifgPeepholeNoProjection<hal_1_1::HalPolicy>(armnn::Compute::GpuAcc); + } + + DOCTEST_TEST_CASE("LstmNoCifgPeepholeProjectionTest_1.1_GpuAcc") + { + LstmNoCifgPeepholeProjection<hal_1_1::HalPolicy>(armnn::Compute::GpuAcc); + } + + DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionBatch2Test_1.1_GpuAcc") + { + LstmCifgPeepholeNoProjectionBatch2<hal_1_1::HalPolicy>(armnn::Compute::GpuAcc); + } + +} +#endif diff --git a/test/1.1/Mean.cpp b/test/1.1/Mean.cpp index c9a5a6d3..70bdc3d3 100644 --- a/test/1.1/Mean.cpp +++ b/test/1.1/Mean.cpp @@ -1,19 +1,15 @@ // -// Copyright © 2017 Arm Ltd. All rights reserved. +// Copyright © 2017, 2022 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // #include "../DriverTestHelpers.hpp" #include "../TestTensor.hpp" -#include "../1.1/HalPolicy.hpp" - -#include <boost/test/data/test_case.hpp> +#include <1.1/HalPolicy.hpp> #include <array> -BOOST_AUTO_TEST_SUITE(MeanTests) - using namespace android::hardware; using namespace driverTestHelpers; using namespace armnn_driver; @@ -24,12 +20,6 @@ using RequestArgument = V1_0::RequestArgument; namespace { -#ifndef ARMCOMPUTECL_ENABLED - static const std::array<armnn::Compute, 1> COMPUTE_DEVICES = {{ armnn::Compute::CpuRef }}; -#else - static const std::array<armnn::Compute, 2> COMPUTE_DEVICES = {{ armnn::Compute::CpuRef, armnn::Compute::GpuAcc }}; -#endif - void MeanTestImpl(const TestTensor& input, const hidl_vec<uint32_t>& axisDimensions, const int32_t* axisValues, @@ -94,64 +84,177 @@ void MeanTestImpl(const TestTensor& input, if (preparedModel.get() != nullptr) { V1_0::ErrorStatus execStatus = Execute(preparedModel, request); - BOOST_TEST(execStatus == V1_0::ErrorStatus::NONE); + DOCTEST_CHECK((int)execStatus == (int)V1_0::ErrorStatus::NONE); } const float* expectedOutputData = expectedOutput.GetData(); for (unsigned int i = 0; i < expectedOutput.GetNumElements(); i++) { - BOOST_TEST(outputData[i] == expectedOutputData[i]); + DOCTEST_CHECK(outputData[i] == expectedOutputData[i]); } } } // anonymous namespace -BOOST_DATA_TEST_CASE(MeanNoKeepDimsTest, COMPUTE_DEVICES) +DOCTEST_TEST_SUITE("MeanTests_CpuRef") { - TestTensor input{ armnn::TensorShape{ 4, 3, 2 }, { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f, - 11.0f, 12.0f, 13.0f, 14.0f, 15.0f, 16.0f, 17.0f, 18.0f, 19.0f, - 20.0f, 21.0f, 22.0f, 23.0f, 24.0f } }; - hidl_vec<uint32_t> axisDimensions = { 2 }; - int32_t axisValues[] = { 0, 1 }; - int32_t keepDims = 0; - TestTensor expectedOutput{ armnn::TensorShape{ 2 }, { 12.0f, 13.0f } }; - - MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, false, sample); -} -BOOST_DATA_TEST_CASE(MeanKeepDimsTest, COMPUTE_DEVICES) -{ - TestTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f } }; - hidl_vec<uint32_t> axisDimensions = { 1 }; - int32_t axisValues[] = { 2 }; - int32_t keepDims = 1; - TestTensor expectedOutput{ armnn::TensorShape{ 1, 1, 1, 2 }, { 2.0f, 2.0f } }; + DOCTEST_TEST_CASE("MeanNoKeepDimsTest_CpuRef") + { + TestTensor input{ armnn::TensorShape{ 4, 3, 2 }, + { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f, + 11.0f, 12.0f, 13.0f, 14.0f, 15.0f, 16.0f, 17.0f, 18.0f, 19.0f, + 20.0f, 21.0f, 22.0f, 23.0f, 24.0f } }; + hidl_vec<uint32_t> axisDimensions = { 2 }; + int32_t axisValues[] = { 0, 1 }; + int32_t keepDims = 0; + TestTensor expectedOutput{ armnn::TensorShape{ 2 }, { 12.0f, 13.0f } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, false, armnn::Compute::CpuRef); + } + + DOCTEST_TEST_CASE("MeanKeepDimsTest_CpuRef") + { + TestTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f } }; + hidl_vec<uint32_t> axisDimensions = { 1 }; + int32_t axisValues[] = { 2 }; + int32_t keepDims = 1; + TestTensor expectedOutput{ armnn::TensorShape{ 1, 1, 1, 2 }, { 2.0f, 2.0f } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, false, armnn::Compute::CpuRef); + } + + DOCTEST_TEST_CASE("MeanFp16EnabledNoKeepDimsTest_CpuRef") + { + TestTensor input{ armnn::TensorShape{ 4, 3, 2 }, + { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f, + 11.0f, 12.0f, 13.0f, 14.0f, 15.0f, 16.0f, 17.0f, 18.0f, 19.0f, + 20.0f, 21.0f, 22.0f, 23.0f, 24.0f } }; + hidl_vec<uint32_t> axisDimensions = { 2 }; + int32_t axisValues[] = { 0, 1 }; + int32_t keepDims = 0; + TestTensor expectedOutput{ armnn::TensorShape{ 2 }, { 12.0f, 13.0f } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::CpuRef); + } + + DOCTEST_TEST_CASE("MeanFp16EnabledKeepDimsTest_CpuRef") + { + TestTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f } }; + hidl_vec<uint32_t> axisDimensions = { 1 }; + int32_t axisValues[] = { 2 }; + int32_t keepDims = 1; + TestTensor expectedOutput{ armnn::TensorShape{ 1, 1, 1, 2 }, { 2.0f, 2.0f } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::CpuRef); + } - MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, false, sample); } -BOOST_DATA_TEST_CASE(MeanFp16NoKeepDimsTest, COMPUTE_DEVICES) +#ifdef ARMCOMPUTECL_ENABLED +DOCTEST_TEST_SUITE("MeanTests_CpuAcc") { - TestTensor input{ armnn::TensorShape{ 4, 3, 2 }, { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f, - 11.0f, 12.0f, 13.0f, 14.0f, 15.0f, 16.0f, 17.0f, 18.0f, 19.0f, - 20.0f, 21.0f, 22.0f, 23.0f, 24.0f } }; - hidl_vec<uint32_t> axisDimensions = { 2 }; - int32_t axisValues[] = { 0, 1 }; - int32_t keepDims = 0; - TestTensor expectedOutput{ armnn::TensorShape{ 2 }, { 12.0f, 13.0f } }; - - MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, sample); + DOCTEST_TEST_CASE("MeanNoKeepDimsTest_CpuAcc") + { + TestTensor input{ armnn::TensorShape{ 4, 3, 2 }, + { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f, + 11.0f, 12.0f, 13.0f, 14.0f, 15.0f, 16.0f, 17.0f, 18.0f, 19.0f, + 20.0f, 21.0f, 22.0f, 23.0f, 24.0f } }; + hidl_vec<uint32_t> axisDimensions = { 2 }; + int32_t axisValues[] = { 0, 1 }; + int32_t keepDims = 0; + TestTensor expectedOutput{ armnn::TensorShape{ 2 }, { 12.0f, 13.0f } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, false, armnn::Compute::CpuAcc); + } + + DOCTEST_TEST_CASE("MeanKeepDimsTest_CpuAcc") + { + TestTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f } }; + hidl_vec<uint32_t> axisDimensions = { 1 }; + int32_t axisValues[] = { 2 }; + int32_t keepDims = 1; + TestTensor expectedOutput{ armnn::TensorShape{ 1, 1, 1, 2 }, { 2.0f, 2.0f } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, false, armnn::Compute::CpuAcc); + } + + DOCTEST_TEST_CASE("MeanFp16EnabledNoKeepDimsTest_CpuAcc") + { + TestTensor input{ armnn::TensorShape{ 4, 3, 2 }, + { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f, + 11.0f, 12.0f, 13.0f, 14.0f, 15.0f, 16.0f, 17.0f, 18.0f, 19.0f, + 20.0f, 21.0f, 22.0f, 23.0f, 24.0f } }; + hidl_vec<uint32_t> axisDimensions = { 2 }; + int32_t axisValues[] = { 0, 1 }; + int32_t keepDims = 0; + TestTensor expectedOutput{ armnn::TensorShape{ 2 }, { 12.0f, 13.0f } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::CpuAcc); + } + + DOCTEST_TEST_CASE("MeanFp16EnabledKeepDimsTest_CpuAcc") + { + TestTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f } }; + hidl_vec<uint32_t> axisDimensions = { 1 }; + int32_t axisValues[] = { 2 }; + int32_t keepDims = 1; + TestTensor expectedOutput{ armnn::TensorShape{ 1, 1, 1, 2 }, { 2.0f, 2.0f } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::CpuAcc); + } } -BOOST_DATA_TEST_CASE(MeanFp16KeepDimsTest, COMPUTE_DEVICES) +DOCTEST_TEST_SUITE("MeanTests_GpuAcc") { - TestTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f } }; - hidl_vec<uint32_t> axisDimensions = { 1 }; - int32_t axisValues[] = { 2 }; - int32_t keepDims = 1; - TestTensor expectedOutput{ armnn::TensorShape{ 1, 1, 1, 2 }, { 2.0f, 2.0f } }; + DOCTEST_TEST_CASE("MeanNoKeepDimsTest_GpuAcc") + { + TestTensor input{ armnn::TensorShape{ 4, 3, 2 }, + { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f, + 11.0f, 12.0f, 13.0f, 14.0f, 15.0f, 16.0f, 17.0f, 18.0f, 19.0f, + 20.0f, 21.0f, 22.0f, 23.0f, 24.0f } }; + hidl_vec<uint32_t> axisDimensions = { 2 }; + int32_t axisValues[] = { 0, 1 }; + int32_t keepDims = 0; + TestTensor expectedOutput{ armnn::TensorShape{ 2 }, { 12.0f, 13.0f } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, false, armnn::Compute::GpuAcc); + } - MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, sample); -} + DOCTEST_TEST_CASE("MeanKeepDimsTest_GpuAcc") + { + TestTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f } }; + hidl_vec<uint32_t> axisDimensions = { 1 }; + int32_t axisValues[] = { 2 }; + int32_t keepDims = 1; + TestTensor expectedOutput{ armnn::TensorShape{ 1, 1, 1, 2 }, { 2.0f, 2.0f } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, false, armnn::Compute::GpuAcc); + } + + DOCTEST_TEST_CASE("MeanFp16EnabledNoKeepDimsTest_GpuAcc") + { + TestTensor input{ armnn::TensorShape{ 4, 3, 2 }, + { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f, + 11.0f, 12.0f, 13.0f, 14.0f, 15.0f, 16.0f, 17.0f, 18.0f, 19.0f, + 20.0f, 21.0f, 22.0f, 23.0f, 24.0f } }; + hidl_vec<uint32_t> axisDimensions = { 2 }; + int32_t axisValues[] = { 0, 1 }; + int32_t keepDims = 0; + TestTensor expectedOutput{ armnn::TensorShape{ 2 }, { 12.0f, 13.0f } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::GpuAcc); + } -BOOST_AUTO_TEST_SUITE_END() + DOCTEST_TEST_CASE("MeanFp16EnabledKeepDimsTest_GpuAcc") + { + TestTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f } }; + hidl_vec<uint32_t> axisDimensions = { 1 }; + int32_t axisValues[] = { 2 }; + int32_t keepDims = 1; + TestTensor expectedOutput{ armnn::TensorShape{ 1, 1, 1, 2 }, { 2.0f, 2.0f } }; + + MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::GpuAcc); + } +} +#endif diff --git a/test/1.1/Transpose.cpp b/test/1.1/Transpose.cpp index 206f9b98..5499e0d6 100644 --- a/test/1.1/Transpose.cpp +++ b/test/1.1/Transpose.cpp @@ -1,24 +1,18 @@ // -// Copyright © 2017 Arm Ltd. All rights reserved. +// Copyright © 2017 Arm Ltd and Contributors. All rights reserved. // SPDX-License-Identifier: MIT // -#include "OperationsUtils.h" #include "../DriverTestHelpers.hpp" #include "../TestTensor.hpp" - -#include "../1.1/HalPolicy.hpp" - -#include <boost/test/unit_test.hpp> -#include <boost/test/data/test_case.hpp> +#include <1.1/HalPolicy.hpp> #include <log/log.h> +#include <OperationsUtils.h> #include <array> #include <cmath> -BOOST_AUTO_TEST_SUITE(TransposeTests) - using namespace android::hardware; using namespace driverTestHelpers; using namespace armnn_driver; @@ -29,12 +23,6 @@ using RequestArgument = V1_0::RequestArgument; namespace { -#ifndef ARMCOMPUTECL_ENABLED - static const std::array<armnn::Compute, 1> COMPUTE_DEVICES = {{ armnn::Compute::CpuRef }}; -#else - static const std::array<armnn::Compute, 2> COMPUTE_DEVICES = {{ armnn::Compute::CpuRef, armnn::Compute::GpuAcc }}; -#endif - void TransposeTestImpl(const TestTensor & inputs, int32_t perm[], const TestTensor & expectedOutputTensor, armnn::Compute computeDevice) { @@ -98,38 +86,100 @@ void TransposeTestImpl(const TestTensor & inputs, int32_t perm[], const float * expectedOutput = expectedOutputTensor.GetData(); for (unsigned int i = 0; i < expectedOutputTensor.GetNumElements(); ++i) { - BOOST_TEST(outdata[i] == expectedOutput[i]); + DOCTEST_CHECK(outdata[i] == expectedOutput[i]); } } } // namespace -BOOST_DATA_TEST_CASE(Transpose , COMPUTE_DEVICES) +DOCTEST_TEST_SUITE("TransposeTests_CpuRef") { - int32_t perm[] = {2, 3, 1, 0}; - TestTensor input{armnn::TensorShape{1, 2, 2, 2},{1, 2, 3, 4, 5, 6, 7, 8}}; - TestTensor expected{armnn::TensorShape{2, 2, 2, 1},{1, 5, 2, 6, 3, 7, 4, 8}}; + DOCTEST_TEST_CASE("Transpose_CpuRef") + { + int32_t perm[] = {2, 3, 1, 0}; + TestTensor input{armnn::TensorShape{1, 2, 2, 2},{1, 2, 3, 4, 5, 6, 7, 8}}; + TestTensor expected{armnn::TensorShape{2, 2, 2, 1},{1, 5, 2, 6, 3, 7, 4, 8}}; + + TransposeTestImpl(input, perm, expected, armnn::Compute::CpuRef); + } + + DOCTEST_TEST_CASE("TransposeNHWCToArmNN_CpuRef") + { + int32_t perm[] = {0, 3, 1, 2}; + TestTensor input{armnn::TensorShape{1, 2, 2, 3},{1, 2, 3, 11, 12, 13, 21, 22, 23, 31, 32, 33}}; + TestTensor expected{armnn::TensorShape{1, 3, 2, 2},{1, 11, 21, 31, 2, 12, 22, 32, 3, 13, 23, 33}}; - TransposeTestImpl(input, perm, expected, sample); + TransposeTestImpl(input, perm, expected, armnn::Compute::CpuRef); + } + DOCTEST_TEST_CASE("TransposeArmNNToNHWC_CpuRef") + { + int32_t perm[] = {0, 2, 3, 1}; + TestTensor input{armnn::TensorShape{1, 2, 2, 2},{1, 2, 3, 4, 5, 6, 7, 8}}; + TestTensor expected{armnn::TensorShape{1, 2, 2, 2},{1, 5, 2, 6, 3, 7, 4, 8}}; + + TransposeTestImpl(input, perm, expected, armnn::Compute::CpuRef); + } } -BOOST_DATA_TEST_CASE(TransposeNHWCToArmNN , COMPUTE_DEVICES) +#ifdef ARMCOMPUTECL_ENABLED +DOCTEST_TEST_SUITE("TransposeTests_CpuAcc") { - int32_t perm[] = {0, 3, 1, 2}; - TestTensor input{armnn::TensorShape{1, 2, 2, 3},{1, 2, 3, 11, 12, 13, 21, 22, 23, 31, 32, 33}}; - TestTensor expected{armnn::TensorShape{1, 3, 2, 2},{1, 11, 21, 31, 2, 12, 22, 32, 3, 13, 23, 33}}; + DOCTEST_TEST_CASE("Transpose_CpuAcc") + { + int32_t perm[] = {2, 3, 1, 0}; + TestTensor input{armnn::TensorShape{1, 2, 2, 2},{1, 2, 3, 4, 5, 6, 7, 8}}; + TestTensor expected{armnn::TensorShape{2, 2, 2, 1},{1, 5, 2, 6, 3, 7, 4, 8}}; + + TransposeTestImpl(input, perm, expected, armnn::Compute::CpuAcc); + } + + DOCTEST_TEST_CASE("TransposeNHWCToArmNN_CpuAcc") + { + int32_t perm[] = {0, 3, 1, 2}; + TestTensor input{armnn::TensorShape{1, 2, 2, 3},{1, 2, 3, 11, 12, 13, 21, 22, 23, 31, 32, 33}}; + TestTensor expected{armnn::TensorShape{1, 3, 2, 2},{1, 11, 21, 31, 2, 12, 22, 32, 3, 13, 23, 33}}; + + TransposeTestImpl(input, perm, expected, armnn::Compute::CpuAcc); + } + + DOCTEST_TEST_CASE("TransposeArmNNToNHWC_CpuAcc") + { + int32_t perm[] = {0, 2, 3, 1}; + TestTensor input{armnn::TensorShape{1, 2, 2, 2},{1, 2, 3, 4, 5, 6, 7, 8}}; + TestTensor expected{armnn::TensorShape{1, 2, 2, 2},{1, 5, 2, 6, 3, 7, 4, 8}}; - TransposeTestImpl(input, perm, expected, sample); + TransposeTestImpl(input, perm, expected, armnn::Compute::CpuAcc); + } } -BOOST_DATA_TEST_CASE(TransposeArmNNToNHWC , COMPUTE_DEVICES) +DOCTEST_TEST_SUITE("TransposeTests_GpuAcc") { - int32_t perm[] = {0, 2, 3, 1}; - TestTensor input{armnn::TensorShape{1, 2, 2, 2},{1, 2, 3, 4, 5, 6, 7, 8}}; - TestTensor expected{armnn::TensorShape{1, 2, 2, 2},{1, 5, 2, 6, 3, 7, 4, 8}}; + DOCTEST_TEST_CASE("Transpose_GpuAcc") + { + int32_t perm[] = {2, 3, 1, 0}; + TestTensor input{armnn::TensorShape{1, 2, 2, 2},{1, 2, 3, 4, 5, 6, 7, 8}}; + TestTensor expected{armnn::TensorShape{2, 2, 2, 1},{1, 5, 2, 6, 3, 7, 4, 8}}; - TransposeTestImpl(input, perm, expected, sample); -} + TransposeTestImpl(input, perm, expected, armnn::Compute::GpuAcc); + } -BOOST_AUTO_TEST_SUITE_END() + DOCTEST_TEST_CASE("TransposeNHWCToArmNN_GpuAcc") + { + int32_t perm[] = {0, 3, 1, 2}; + TestTensor input{armnn::TensorShape{1, 2, 2, 3},{1, 2, 3, 11, 12, 13, 21, 22, 23, 31, 32, 33}}; + TestTensor expected{armnn::TensorShape{1, 3, 2, 2},{1, 11, 21, 31, 2, 12, 22, 32, 3, 13, 23, 33}}; + + TransposeTestImpl(input, perm, expected, armnn::Compute::GpuAcc); + } + + DOCTEST_TEST_CASE("TransposeArmNNToNHWC_GpuAcc") + { + int32_t perm[] = {0, 2, 3, 1}; + TestTensor input{armnn::TensorShape{1, 2, 2, 2},{1, 2, 3, 4, 5, 6, 7, 8}}; + TestTensor expected{armnn::TensorShape{1, 2, 2, 2},{1, 5, 2, 6, 3, 7, 4, 8}}; + + TransposeTestImpl(input, perm, expected, armnn::Compute::GpuAcc); + } +} +#endif |