IVGCVSW-6428 Remove asserts

 * Changed asserts to check for errors and return appropriate values or
   throw exceptions
 * Changed unit tests to use Doctest's long macro names as the short
   macro names clashed with Android's Logging macros
 * Removed unused #includes
 * Clarified ambiguous #includes

Signed-off-by: Mike Kelly <mike.kelly@arm.com>
Change-Id: Ice92a37590df727fd581d3be5ff2716665f26a13

4 files changed, 67 insertions, 62 deletions

diff --git a/test/1.1/Convolution2D.cpp b/test/1.1/Convolution2D.cpp
index 0daa4728..4601f760 100644
--- a/test/1.1/Convolution2D.cpp
+++ b/test/1.1/Convolution2D.cpp
@@ -1,19 +1,14 @@
 //
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
 // SPDX-License-Identifier: MIT
 //
 
-#include "../DriverTestHelpers.hpp"
 #include "../Convolution2D.hpp"
-#include "../../1.1/HalPolicy.hpp"
 
-#include <doctest/doctest.h>
 #include <log/log.h>
 
 #include <OperationsUtils.h>
 
-
-
 using namespace android::hardware;
 using namespace driverTestHelpers;
 using namespace armnn_driver;
@@ -30,25 +25,25 @@ void SetModelFp16Flag(V1_1::Model& model, bool fp16Enabled)
 } // namespace driverTestHelpers
 
 
-TEST_SUITE("Convolution2DTests_1.1")
+DOCTEST_TEST_SUITE("Convolution2DTests_1.1")
 {
 
-TEST_CASE("ConvValidPadding_Hal_1_1")
+DOCTEST_TEST_CASE("ConvValidPadding_Hal_1_1")
 {
     PaddingTestImpl<hal_1_1::HalPolicy>(android::nn::kPaddingValid);
 }
 
-TEST_CASE("ConvSamePadding_Hal_1_1")
+DOCTEST_TEST_CASE("ConvSamePadding_Hal_1_1")
 {
     PaddingTestImpl<hal_1_1::HalPolicy>(android::nn::kPaddingSame);
 }
 
-TEST_CASE("ConvValidPaddingFp16Flag_Hal_1_1")
+DOCTEST_TEST_CASE("ConvValidPaddingFp16Flag_Hal_1_1")
 {
     PaddingTestImpl<hal_1_1::HalPolicy>(android::nn::kPaddingValid, true);
 }
 
-TEST_CASE("ConvSamePaddingFp16Flag_Hal_1_1")
+DOCTEST_TEST_CASE("ConvSamePaddingFp16Flag_Hal_1_1")
 {
     PaddingTestImpl<hal_1_1::HalPolicy>(android::nn::kPaddingSame, true);
 }
diff --git a/test/1.1/Lstm.cpp b/test/1.1/Lstm.cpp
index 2699ec4c..cbdf6b14 100644
--- a/test/1.1/Lstm.cpp
+++ b/test/1.1/Lstm.cpp
@@ -1,5 +1,5 @@
 //
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
 // SPDX-License-Identifier: MIT
 //
 
@@ -7,44 +7,54 @@
 
 using namespace armnn_driver;
 
-TEST_SUITE("LstmTests_1.1_CpuRef")
+DOCTEST_TEST_SUITE("LstmTests_1.1_CpuRef")
 {
-    TEST_CASE("LstmNoCifgNoPeepholeNoProjectionTest_1.1_armnn::Compute::CpuRef")
+
+    DOCTEST_TEST_CASE("LstmNoCifgNoPeepholeNoProjectionTest_1.1_armnn::Compute::CpuRef")
     {
         LstmNoCifgNoPeepholeNoProjection<hal_1_1::HalPolicy>(armnn::Compute::CpuRef);
     }
-    TEST_CASE("LstmCifgPeepholeNoProjectionTest_1.1_CpuRef")
+
+    DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionTest_1.1_CpuRef")
     {
         LstmCifgPeepholeNoProjection<hal_1_1::HalPolicy>(armnn::Compute::CpuRef);
     }
-    TEST_CASE("LstmNoCifgPeepholeProjectionTest_1.1_CpuRef")
+
+    DOCTEST_TEST_CASE("LstmNoCifgPeepholeProjectionTest_1.1_CpuRef")
     {
         LstmNoCifgPeepholeProjection<hal_1_1::HalPolicy>(armnn::Compute::CpuRef);
     }
-    TEST_CASE("LstmCifgPeepholeNoProjectionBatch2Test_1.1_CpuRef")
+
+    DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionBatch2Test_1.1_CpuRef")
     {
         LstmCifgPeepholeNoProjectionBatch2<hal_1_1::HalPolicy>(armnn::Compute::CpuRef);
     }
+
 }
 
 #if defined(ARMCOMPUTECL_ENABLED)
-TEST_SUITE("LstmTests_1.1_GpuAcc")
+DOCTEST_TEST_SUITE("LstmTests_1.1_GpuAcc")
 {
-    TEST_CASE("LstmNoCifgNoPeepholeNoProjectionTest_1.1_GpuAcc")
+
+    DOCTEST_TEST_CASE("LstmNoCifgNoPeepholeNoProjectionTest_1.1_GpuAcc")
     {
         LstmNoCifgNoPeepholeNoProjection<hal_1_1::HalPolicy>(armnn::Compute::GpuAcc);
     }
-    TEST_CASE("LstmCifgPeepholeNoProjectionTest_1.1_GpuAcc")
+
+    DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionTest_1.1_GpuAcc")
     {
         LstmCifgPeepholeNoProjection<hal_1_1::HalPolicy>(armnn::Compute::GpuAcc);
     }
-    TEST_CASE("LstmNoCifgPeepholeProjectionTest_1.1_GpuAcc")
+
+    DOCTEST_TEST_CASE("LstmNoCifgPeepholeProjectionTest_1.1_GpuAcc")
     {
         LstmNoCifgPeepholeProjection<hal_1_1::HalPolicy>(armnn::Compute::GpuAcc);
     }
-    TEST_CASE("LstmCifgPeepholeNoProjectionBatch2Test_1.1_GpuAcc")
+
+    DOCTEST_TEST_CASE("LstmCifgPeepholeNoProjectionBatch2Test_1.1_GpuAcc")
     {
         LstmCifgPeepholeNoProjectionBatch2<hal_1_1::HalPolicy>(armnn::Compute::GpuAcc);
     }
+
 }
 #endif
diff --git a/test/1.1/Mean.cpp b/test/1.1/Mean.cpp
index c7c5a9b5..34c29bad 100644
--- a/test/1.1/Mean.cpp
+++ b/test/1.1/Mean.cpp
@@ -1,14 +1,12 @@
 //
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
 // SPDX-License-Identifier: MIT
 //
 
 #include "../DriverTestHelpers.hpp"
 #include "../TestTensor.hpp"
 
-#include "../1.1/HalPolicy.hpp"
-
-#include <doctest/doctest.h>
+#include <1.1/HalPolicy.hpp>
 
 #include <array>
 
@@ -86,21 +84,22 @@ void MeanTestImpl(const TestTensor& input,
     if (preparedModel.get() != nullptr)
     {
         V1_0::ErrorStatus execStatus = Execute(preparedModel, request);
-        CHECK((int)execStatus == (int)V1_0::ErrorStatus::NONE);
+        DOCTEST_CHECK((int)execStatus == (int)V1_0::ErrorStatus::NONE);
     }
 
     const float* expectedOutputData = expectedOutput.GetData();
     for (unsigned int i = 0; i < expectedOutput.GetNumElements(); i++)
     {
-        CHECK(outputData[i] == expectedOutputData[i]);
+        DOCTEST_CHECK(outputData[i] == expectedOutputData[i]);
     }
 }
 
 } // anonymous namespace
 
-TEST_SUITE("MeanTests_CpuRef")
+DOCTEST_TEST_SUITE("MeanTests_CpuRef")
 {
-    TEST_CASE("MeanNoKeepDimsTest_CpuRef")
+
+    DOCTEST_TEST_CASE("MeanNoKeepDimsTest_CpuRef")
     {
         TestTensor input{ armnn::TensorShape{ 4, 3, 2 },
                           { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f,
@@ -114,7 +113,7 @@ TEST_SUITE("MeanTests_CpuRef")
         MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, false, armnn::Compute::CpuRef);
     }
 
-    TEST_CASE("MeanKeepDimsTest_CpuRef")
+    DOCTEST_TEST_CASE("MeanKeepDimsTest_CpuRef")
     {
         TestTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f } };
         hidl_vec<uint32_t> axisDimensions = { 1 };
@@ -125,7 +124,7 @@ TEST_SUITE("MeanTests_CpuRef")
         MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, false, armnn::Compute::CpuRef);
     }
 
-    TEST_CASE("MeanFp16NoKeepDimsTest_CpuRef")
+    DOCTEST_TEST_CASE("MeanFp16NoKeepDimsTest_CpuRef")
     {
         TestTensor input{ armnn::TensorShape{ 4, 3, 2 },
                           { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f,
@@ -139,7 +138,7 @@ TEST_SUITE("MeanTests_CpuRef")
         MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::CpuRef);
     }
 
-    TEST_CASE("MeanFp16KeepDimsTest_CpuRef")
+    DOCTEST_TEST_CASE("MeanFp16KeepDimsTest_CpuRef")
     {
         TestTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f } };
         hidl_vec<uint32_t> axisDimensions = { 1 };
@@ -149,12 +148,13 @@ TEST_SUITE("MeanTests_CpuRef")
 
         MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::CpuRef);
     }
+
 }
 
 #ifdef ARMCOMPUTECL_ENABLED
-TEST_SUITE("MeanTests_CpuAcc")
+DOCTEST_TEST_SUITE("MeanTests_CpuAcc")
 {
-    TEST_CASE("MeanNoKeepDimsTest_CpuAcc")
+    DOCTEST_TEST_CASE("MeanNoKeepDimsTest_CpuAcc")
     {
         TestTensor input{ armnn::TensorShape{ 4, 3, 2 },
                           { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f,
@@ -168,7 +168,7 @@ TEST_SUITE("MeanTests_CpuAcc")
         MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, false, armnn::Compute::CpuAcc);
     }
 
-    TEST_CASE("MeanKeepDimsTest_CpuAcc")
+    DOCTEST_TEST_CASE("MeanKeepDimsTest_CpuAcc")
     {
         TestTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f } };
         hidl_vec<uint32_t> axisDimensions = { 1 };
@@ -179,7 +179,7 @@ TEST_SUITE("MeanTests_CpuAcc")
         MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, false, armnn::Compute::CpuAcc);
     }
 
-    TEST_CASE("MeanFp16NoKeepDimsTest_CpuAcc")
+    DOCTEST_TEST_CASE("MeanFp16NoKeepDimsTest_CpuAcc")
     {
         TestTensor input{ armnn::TensorShape{ 4, 3, 2 },
                           { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f,
@@ -193,7 +193,7 @@ TEST_SUITE("MeanTests_CpuAcc")
         MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::CpuAcc);
     }
 
-    TEST_CASE("MeanFp16KeepDimsTest_CpuAcc")
+    DOCTEST_TEST_CASE("MeanFp16KeepDimsTest_CpuAcc")
     {
         TestTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f } };
         hidl_vec<uint32_t> axisDimensions = { 1 };
@@ -205,9 +205,9 @@ TEST_SUITE("MeanTests_CpuAcc")
     }
 }
 
-TEST_SUITE("MeanTests_GpuAcc")
+DOCTEST_TEST_SUITE("MeanTests_GpuAcc")
 {
-    TEST_CASE("MeanNoKeepDimsTest_GpuAcc")
+    DOCTEST_TEST_CASE("MeanNoKeepDimsTest_GpuAcc")
     {
         TestTensor input{ armnn::TensorShape{ 4, 3, 2 },
                           { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f,
@@ -221,7 +221,7 @@ TEST_SUITE("MeanTests_GpuAcc")
         MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, false, armnn::Compute::GpuAcc);
     }
 
-    TEST_CASE("MeanKeepDimsTest_GpuAcc")
+    DOCTEST_TEST_CASE("MeanKeepDimsTest_GpuAcc")
     {
         TestTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f } };
         hidl_vec<uint32_t> axisDimensions = { 1 };
@@ -232,7 +232,7 @@ TEST_SUITE("MeanTests_GpuAcc")
         MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, false, armnn::Compute::GpuAcc);
     }
 
-    TEST_CASE("MeanFp16NoKeepDimsTest_GpuAcc")
+    DOCTEST_TEST_CASE("MeanFp16NoKeepDimsTest_GpuAcc")
     {
         TestTensor input{ armnn::TensorShape{ 4, 3, 2 },
                           { 1.0f, 2.0f, 3.0f, 4.0f, 5.0f, 6.0f, 7.0f, 8.0f, 9.0f, 10.0f,
@@ -246,7 +246,7 @@ TEST_SUITE("MeanTests_GpuAcc")
         MeanTestImpl(input, axisDimensions, axisValues, keepDims, expectedOutput, true, armnn::Compute::GpuAcc);
     }
 
-    TEST_CASE("MeanFp16KeepDimsTest_GpuAcc")
+    DOCTEST_TEST_CASE("MeanFp16KeepDimsTest_GpuAcc")
     {
         TestTensor input{ armnn::TensorShape{ 1, 1, 3, 2 }, { 1.0f, 1.0f, 2.0f, 2.0f, 3.0f, 3.0f } };
         hidl_vec<uint32_t> axisDimensions = { 1 };
diff --git a/test/1.1/Transpose.cpp b/test/1.1/Transpose.cpp
index 4c4dc349..5499e0d6 100644
--- a/test/1.1/Transpose.cpp
+++ b/test/1.1/Transpose.cpp
@@ -1,17 +1,14 @@
 //
-// Copyright © 2017 Arm Ltd. All rights reserved.
+// Copyright © 2017 Arm Ltd and Contributors. All rights reserved.
 // SPDX-License-Identifier: MIT
 //
-#include "OperationsUtils.h"
 
 #include "../DriverTestHelpers.hpp"
 #include "../TestTensor.hpp"
-
-#include "../1.1/HalPolicy.hpp"
-
-#include <doctest/doctest.h>
+#include <1.1/HalPolicy.hpp>
 
 #include <log/log.h>
+#include <OperationsUtils.h>
 
 #include <array>
 #include <cmath>
@@ -89,15 +86,15 @@ void TransposeTestImpl(const TestTensor & inputs, int32_t perm[],
     const float * expectedOutput = expectedOutputTensor.GetData();
     for (unsigned int i = 0; i < expectedOutputTensor.GetNumElements(); ++i)
     {
-        CHECK(outdata[i] == expectedOutput[i]);
+        DOCTEST_CHECK(outdata[i] == expectedOutput[i]);
     }
 }
 
 } // namespace
 
-TEST_SUITE("TransposeTests_CpuRef")
+DOCTEST_TEST_SUITE("TransposeTests_CpuRef")
 {
-    TEST_CASE("Transpose_CpuRef")
+    DOCTEST_TEST_CASE("Transpose_CpuRef")
     {
         int32_t perm[] = {2, 3, 1, 0};
         TestTensor input{armnn::TensorShape{1, 2, 2, 2},{1, 2, 3, 4, 5, 6, 7, 8}};
@@ -106,7 +103,7 @@ TEST_SUITE("TransposeTests_CpuRef")
         TransposeTestImpl(input, perm, expected, armnn::Compute::CpuRef);
     }
 
-    TEST_CASE("TransposeNHWCToArmNN_CpuRef")
+    DOCTEST_TEST_CASE("TransposeNHWCToArmNN_CpuRef")
     {
         int32_t perm[] = {0, 3, 1, 2};
         TestTensor input{armnn::TensorShape{1, 2, 2, 3},{1, 2, 3, 11, 12, 13, 21, 22, 23, 31, 32, 33}};
@@ -114,7 +111,7 @@ TEST_SUITE("TransposeTests_CpuRef")
 
         TransposeTestImpl(input, perm, expected, armnn::Compute::CpuRef);
     }
-    TEST_CASE("TransposeArmNNToNHWC_CpuRef")
+    DOCTEST_TEST_CASE("TransposeArmNNToNHWC_CpuRef")
     {
         int32_t perm[] = {0, 2, 3, 1};
         TestTensor input{armnn::TensorShape{1, 2, 2, 2},{1, 2, 3, 4, 5, 6, 7, 8}};
@@ -125,9 +122,9 @@ TEST_SUITE("TransposeTests_CpuRef")
 }
 
 #ifdef ARMCOMPUTECL_ENABLED
-TEST_SUITE("TransposeTests_CpuAcc")
+DOCTEST_TEST_SUITE("TransposeTests_CpuAcc")
 {
-    TEST_CASE("Transpose_CpuAcc")
+    DOCTEST_TEST_CASE("Transpose_CpuAcc")
     {
         int32_t perm[] = {2, 3, 1, 0};
         TestTensor input{armnn::TensorShape{1, 2, 2, 2},{1, 2, 3, 4, 5, 6, 7, 8}};
@@ -136,7 +133,7 @@ TEST_SUITE("TransposeTests_CpuAcc")
         TransposeTestImpl(input, perm, expected, armnn::Compute::CpuAcc);
     }
 
-    TEST_CASE("TransposeNHWCToArmNN_CpuAcc")
+    DOCTEST_TEST_CASE("TransposeNHWCToArmNN_CpuAcc")
     {
         int32_t perm[] = {0, 3, 1, 2};
         TestTensor input{armnn::TensorShape{1, 2, 2, 3},{1, 2, 3, 11, 12, 13, 21, 22, 23, 31, 32, 33}};
@@ -144,7 +141,8 @@ TEST_SUITE("TransposeTests_CpuAcc")
 
         TransposeTestImpl(input, perm, expected, armnn::Compute::CpuAcc);
     }
-    TEST_CASE("TransposeArmNNToNHWC_CpuAcc")
+
+    DOCTEST_TEST_CASE("TransposeArmNNToNHWC_CpuAcc")
     {
         int32_t perm[] = {0, 2, 3, 1};
         TestTensor input{armnn::TensorShape{1, 2, 2, 2},{1, 2, 3, 4, 5, 6, 7, 8}};
@@ -153,9 +151,10 @@ TEST_SUITE("TransposeTests_CpuAcc")
         TransposeTestImpl(input, perm, expected, armnn::Compute::CpuAcc);
     }
 }
-TEST_SUITE("TransposeTests_GpuAcc")
+
+DOCTEST_TEST_SUITE("TransposeTests_GpuAcc")
 {
-    TEST_CASE("Transpose_GpuAcc")
+    DOCTEST_TEST_CASE("Transpose_GpuAcc")
     {
         int32_t perm[] = {2, 3, 1, 0};
         TestTensor input{armnn::TensorShape{1, 2, 2, 2},{1, 2, 3, 4, 5, 6, 7, 8}};
@@ -164,7 +163,7 @@ TEST_SUITE("TransposeTests_GpuAcc")
         TransposeTestImpl(input, perm, expected, armnn::Compute::GpuAcc);
     }
 
-    TEST_CASE("TransposeNHWCToArmNN_GpuAcc")
+    DOCTEST_TEST_CASE("TransposeNHWCToArmNN_GpuAcc")
     {
         int32_t perm[] = {0, 3, 1, 2};
         TestTensor input{armnn::TensorShape{1, 2, 2, 3},{1, 2, 3, 11, 12, 13, 21, 22, 23, 31, 32, 33}};
@@ -172,7 +171,8 @@ TEST_SUITE("TransposeTests_GpuAcc")
 
         TransposeTestImpl(input, perm, expected, armnn::Compute::GpuAcc);
     }
-    TEST_CASE("TransposeArmNNToNHWC_GpuAcc")
+
+    DOCTEST_TEST_CASE("TransposeArmNNToNHWC_GpuAcc")
     {
         int32_t perm[] = {0, 2, 3, 1};
         TestTensor input{armnn::TensorShape{1, 2, 2, 2},{1, 2, 3, 4, 5, 6, 7, 8}};