From cf87f509fc23d02c56569f794a3fb59e1b8be277 Mon Sep 17 00:00:00 2001 From: Michele Di Giorgio Date: Tue, 2 Feb 2021 14:59:09 +0000 Subject: Tweak scheduling use of SQDMULH in quantized AVG pooling Resolves COMPMID-4195 Change-Id: Ie5116c1ddddccafba40432fd4b5245bb27890a88 Signed-off-by: Michele Di Giorgio Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/4997 Reviewed-by: TeresaARM Reviewed-by: Manuel Bottini Comments-Addressed: Arm Jenkins Tested-by: Arm Jenkins --- .../generic.cpp | 73 +++++++++++----------- 1 file changed, 36 insertions(+), 37 deletions(-) (limited to 'src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp') diff --git a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp index 7246b69f06..f288a4119c 100644 --- a/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp +++ b/src/core/NEON/kernels/arm_conv/pooling/kernels/a64_s8q_nhwc_avg_generic_depthfirst/generic.cpp @@ -23,7 +23,6 @@ */ #include "pooling.hpp" -#include #include #include #include @@ -42,10 +41,10 @@ namespace { constexpr RescaleParams rescale_params[8] = { {0x40000000, -0}, // 1/2 - {0x55555555, -1}, // 1/3 + {0x55555556, -1}, // 1/3 {0x40000000, -1}, // 1/4 {0x66666666, -2}, // 1/5 - {0x55555555, -2}, // 1/6 + {0x55555556, -2}, // 1/6 {0x49249249, -2}, // 1/7 {0x40000000, -2}, // 1/8 {0x71c71c72, -3}, // 1/9 @@ -140,10 +139,10 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "movi v0.4s, #0x0\n" "cbz x22, 4f\n" "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" - "subs x22, x22, #0x1\n" "ldr q31, [x21, x26]\n" + "add x19, x19, #0x10\n" "ldr q30, [x20, x26]\n" + "subs x22, x22, #0x1\n" "ldr q29, [x21, x25]\n" "ldr q28, [x20, x25]\n" "ldr q27, [x21, x24]\n" @@ -156,24 +155,24 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "ldp x21, x20, [x19, #0x0]\n" "add x19, x19, #0x10\n" "saddl2 v22.8h, v31.16b, v30.16b\n" - "subs x22, x22, #0x1\n" - "saddl v21.8h, v29.8b, v28.8b\n" "ldr q31, [x21, x26]\n" + "saddl v21.8h, v29.8b, v28.8b\n" + "subs x22, x22, #0x1\n" "saddl2 v20.8h, v29.16b, v28.16b\n" - "saddl v19.8h, v27.8b, v26.8b\n" "ldr q30, [x20, x26]\n" - "saddl2 v18.8h, v27.16b, v26.16b\n" + "saddl v19.8h, v27.8b, v26.8b\n" "ldr q29, [x21, x25]\n" - "saddl v17.8h, v25.8b, v24.8b\n" + "saddl2 v18.8h, v27.16b, v26.16b\n" "ldr q28, [x20, x25]\n" - "saddl2 v16.8h, v25.16b, v24.16b\n" + "saddl v17.8h, v25.8b, v24.8b\n" "ldr q27, [x21, x24]\n" - "saddw v15.4s, v15.4s, v23.4h\n" + "saddl2 v16.8h, v25.16b, v24.16b\n" "ldr q26, [x20, x24]\n" - "saddw2 v14.4s, v14.4s, v23.8h\n" + "saddw v15.4s, v15.4s, v23.4h\n" "ldr q25, [x21, x23]\n" - "saddw v13.4s, v13.4s, v22.4h\n" + "saddw2 v14.4s, v14.4s, v23.8h\n" "ldr q24, [x20, x23]\n" + "saddw v13.4s, v13.4s, v22.4h\n" "saddw2 v12.4s, v12.4s, v22.8h\n" "saddw v11.4s, v11.4s, v21.4h\n" "saddw2 v10.4s, v10.4s, v21.8h\n" @@ -220,19 +219,19 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "ldr x21, [x19], #0x8\n" "subs x20, x20, #0x1\n" "ldr q31, [x21, x26]\n" - "sxtl v16.8h, v31.8b\n" + "sxtl v23.8h, v31.8b\n" "ldr q29, [x21, x25]\n" "sxtl2 v22.8h, v31.16b\n" "ldr q27, [x21, x24]\n" "ldr q25, [x21, x23]\n" - "saddw v15.4s, v15.4s, v16.4h\n" - "saddw2 v14.4s, v14.4s, v16.8h\n" "sxtl v21.8h, v29.8b\n" "sxtl2 v20.8h, v29.16b\n" "sxtl v19.8h, v27.8b\n" "sxtl2 v18.8h, v27.16b\n" "sxtl v17.8h, v25.8b\n" "sxtl2 v16.8h, v25.16b\n" + "saddw v15.4s, v15.4s, v23.4h\n" + "saddw2 v14.4s, v14.4s, v23.8h\n" "saddw v13.4s, v13.4s, v22.4h\n" "saddw2 v12.4s, v12.4s, v22.8h\n" "saddw v11.4s, v11.4s, v21.4h\n" @@ -339,22 +338,22 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "uzp1 v23.16b, v15.16b, v14.16b\n" "uzp1 v16.16b, v13.16b, v12.16b\n" "uzp1 v22.16b, v11.16b, v10.16b\n" - "uzp1 v18.16b, v9.16b, v8.16b\n" - "uzp1 v21.16b, v7.16b, v6.16b\n" + "uzp1 v21.16b, v9.16b, v8.16b\n" + "uzp1 v20.16b, v7.16b, v6.16b\n" "uzp1 v17.16b, v5.16b, v4.16b\n" - "uzp1 v20.16b, v3.16b, v2.16b\n" - "uzp1 v19.16b, v1.16b, v0.16b\n" + "uzp1 v19.16b, v3.16b, v2.16b\n" + "uzp1 v18.16b, v1.16b, v0.16b\n" "uzp1 v16.16b, v23.16b, v16.16b\n" "str q16, [%x[outptr], x26]\n" - "uzp1 v18.16b, v22.16b, v18.16b\n" - "uzp1 v17.16b, v21.16b, v17.16b\n" + "uzp1 v16.16b, v22.16b, v21.16b\n" "add x26, x26, #0x40\n" - "uzp1 v16.16b, v20.16b, v19.16b\n" - "str q18, [%x[outptr], x25]\n" - "str q17, [%x[outptr], x24]\n" - "str q16, [%x[outptr], x23]\n" + "uzp1 v17.16b, v20.16b, v17.16b\n" + "str q16, [%x[outptr], x25]\n" + "uzp1 v16.16b, v19.16b, v18.16b\n" "add x25, x25, #0x40\n" + "str q17, [%x[outptr], x24]\n" "add x24, x24, #0x40\n" + "str q16, [%x[outptr], x23]\n" "add x23, x23, #0x40\n" "bge 1b\n" "cbz %x[n_channels], 43f\n" @@ -370,19 +369,19 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "movi v12.4s, #0x0\n" "cbz x22, 11f\n" "ldp x21, x20, [x19, #0x0]\n" - "add x19, x19, #0x10\n" - "subs x22, x22, #0x1\n" "ldr q31, [x21, x26]\n" + "add x19, x19, #0x10\n" "ldr q30, [x20, x26]\n" + "subs x22, x22, #0x1\n" "beq 10f\n" "9:" // Single vector of channels: Loop: 2 inputs loop "saddl v23.8h, v31.8b, v30.8b\n" "ldp x21, x20, [x19, #0x0]\n" "add x19, x19, #0x10\n" "saddl2 v22.8h, v31.16b, v30.16b\n" - "subs x22, x22, #0x1\n" - "saddw v15.4s, v15.4s, v23.4h\n" "ldr q31, [x21, x26]\n" + "saddw v15.4s, v15.4s, v23.4h\n" + "subs x22, x22, #0x1\n" "saddw2 v14.4s, v14.4s, v23.8h\n" "ldr q30, [x20, x26]\n" "saddw v13.4s, v13.4s, v22.4h\n" @@ -402,10 +401,10 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "ldr x21, [x19], #0x8\n" "subs x20, x20, #0x1\n" "ldr q31, [x21, x26]\n" - "sxtl v16.8h, v31.8b\n" + "sxtl v23.8h, v31.8b\n" "sxtl2 v22.8h, v31.16b\n" - "saddw v15.4s, v15.4s, v16.4h\n" - "saddw2 v14.4s, v14.4s, v16.8h\n" + "saddw v15.4s, v15.4s, v23.4h\n" + "saddw2 v14.4s, v14.4s, v23.8h\n" "saddw v13.4s, v13.4s, v22.4h\n" "saddw2 v12.4s, v12.4s, v22.8h\n" "bgt 12b\n" @@ -580,11 +579,11 @@ void a64_s8q_nhwc_avg_generic_depthfirst_impl( "tbz %x[n_channels], #0, 33f\n" "ldr b31, [x21], #0x1\n" "33:" // Oddments: Single input loop: Load: Bit 3: End - "sxtl v16.8h, v31.8b\n" + "sxtl v23.8h, v31.8b\n" "subs x20, x20, #0x1\n" "sxtl2 v22.8h, v31.16b\n" - "saddw v15.4s, v15.4s, v16.4h\n" - "saddw2 v14.4s, v14.4s, v16.8h\n" + "saddw v15.4s, v15.4s, v23.4h\n" + "saddw2 v14.4s, v14.4s, v23.8h\n" "saddw v13.4s, v13.4s, v22.4h\n" "saddw2 v12.4s, v12.4s, v22.8h\n" "bgt 25b\n" -- cgit v1.2.1