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kernels
Change-Id: I98183f95814442b6f3dbb67a1bdae99df05b9b01
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BoxWithNMSLimitKernel
COMPMID-1792: Accuracy issue in CLGenerateProposals
This patch does the following:
- Some fixes for GenerateProposals function and tests
- Adapting BoxWithNMSLimitKernel to only accept U32 tensors as keeps_size
- Update 3rdparty
- Adds a small tolerance for a GenerateProposals test
Change-Id: Ia8ec1cdfe941fe05003645e86deb9ea6a6044d74
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Introduced F32 accumulation for F16 winograd gemm and output transform
WinogradConvolution will be available for F16 only if fast math flag is enabled
Change-Id: I215593c205236a0f9669218437bb40b184ec6a4f
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Change-Id: I99e1c3939cfea4b9cb0ddfa313706f31b213ca89
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Change-Id: Ibc8d903c8d3c97b51dc8a3344197b56ad9d6c00e
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Change-Id: Ia8d4e46ce5d9bb366af15726bc208dc14583c6ae
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Change-Id: I69e995973597ba3927d29e4f6ed5438560e53d77
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In case of CIFG optimisation scratch buffer should have a size of
[batch_size, num_units * 3] else [batch_size, num_units * 4].
Change-Id: I43e46f7b52e791472f1196f36e9142240ba76c5c
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Change-Id: Ib0798cc17496b7817f5b5769b25d98913a33a69d
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Change-Id: I5bf5d751ec7c02d96c26a769f49d03ea23a248b7
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and 8 tensors (Part 1)
Creating special cases for concatening 2 and 4 tensors.
Change-Id: I6a739a494ae45011acb65369e353f9ef96970b90
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NEGEMMLowpQuantizeDownInt32ToUint8ScaleByFixedPoint
Change-Id: I1d5bc4d24059917f9ddef0873dd3043b1f2320a8
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-Use raw string literals in regexp in CPUUtils.cpp
-Avoid implicit cast bool->int
Change-Id: I45a403ab8d0be02bb8dec267fe59545ad1074292
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Change-Id: I93b14106cda8a1f640cf5acf120d31e2ebdaf495
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Some systems don't have enough memory to run the VGG networks, for example
on systems with only 2GB memory the VGG example fails throwing a bad_alloc exception.
This patch introduces the concept of global memory policy in ACL, the policy
is a mechanism which could be used by the library's functions to try to reduce
memory consumption on systems with limited memory.
In this specific case the VGG examples set the policy to MINIMIZE. The GEMM
function checks if the policy is MINIMIZE and in this case does not use the
pretransposed weights path as this requires considerable more memory.
Change-Id: I53abc3c9c64d045d8306793ffc9d24b28e228b7b
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Change-Id: I57bbdbef85d1f6e8cf1d13324f9cc38a3e3f0cc3
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-Uses output quantization information for the activation layer.
-Updates checks for BoundedRelu at CL side.
Change-Id: I0447860e90f1c89b67b9ace3c8daad713f6c64e0
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Change-Id: I953f3b63aa4910650a1a3f6faea31beb4f6f376a
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CLGEMMLowpQuantizeDownInt32ToUint8ScaleByFloat
Since we perform an element-wise operation, it is not necessary to pass the output_depth3d.
Change-Id: Ibfa07a0706e902acf59b444aa61e18a348162ea9
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The issue was related to CLIm2Col when the number of input channels was less than
the number of elements processed by each thread.
The bug has been fixed in the validate_and_configure_window() function setting the correct number of elements accessed
in the output tensor.
Also fixed an issue GEMM3D when we have a single output channel
Change-Id: I094292d0c7662599c4a4c3916ec5f5821df5faef
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Change-Id: I86679adff556b6ffc9929b35cbf1b59b3958bdb1
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Change-Id: I6d5f91579850906e1eb973ff6c5612195255e631
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Change-Id: I68c648a5246fcdc67a496602089f93d65eb1d601
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ArmNN reported an issue with padding in CLLSTMLayer. This was due to the fact
that some tensors were allocated before they were passed to some configure
functions which attempted to change the padding requirement on already allocated
memory.
Also, increase tolerance on number of mismatches for CLBBoxTransform FP16.
Change-Id: Iad75b012be895693d0e553f3ab85f1ca7144e882
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Change-Id: I5aae537372bf797fbb2a2bae81038f8963b041a9
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Change-Id: Iac6a95ba7f388e65b7f1c8865c3e9bf289b233ea
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155490
Reviewed-by: Anthony Barbier <anthony.barbier@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: I0cf221c706c3d957423941d3aa9a9262dcb00c00
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155593
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: Anthony Barbier <anthony.barbier@arm.com>
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OpenCL
COMPMID-1424 - Add dot product support for CLDepthwise QASYMM8 3x3 NHWC non-unit stride
With this patch we are able to improve the performance of MobileNet v1-qasymm8 by 37 %
Tried to use the dot product instruction in CLDepthwise QASYMM8 3x3 NHWC non-unit stride
but I have not seen any benefit (maybe because we have few arithemtic operation and we
do not have more load instructions). However Depthwise convolution has been improved by
30%
Change-Id: Id768a99c2e53a04276707e427af5d0ec93419ada
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155082
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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Change-Id: Ie1bcdd9dca2dc3b26003790a19cc80bb953385b2
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155373
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: Ibb6b0ceed19111c01fcc96eb50e461f9811b61b9
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155260
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: I7bd4a8ce81483ba56686b765ca3caabebe42882d
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155000
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
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Change-Id: Ic8312a5b6790aa7cd4468d42f08d557ad40e9441
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154570
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
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Change-Id: Id964d9068e18aaa13ab8adcbf7a9375b034ea6c3
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154651
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
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Change-Id: I91865506166951b3bf7f06a0b2d4cde925cfefb6
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/153447
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
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NEGEMMConvolutionLayer.
Change-Id: Iea5f2c5bcac8051c4c7655a6eabb2c43772eb31f
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154104
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
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Change-Id: Iae22554d5fe893fd22a000eab5bfd8275ea06eb3
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154102
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: I146936c9e98b343496a4b61cdbadf0eaa38e885a
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154008
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
Reviewed-by: Giuseppe Rossini <giuseppe.rossini@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: Id974efad304c2513b8824a6561ad45ee60b9e7fb
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/153763
Reviewed-by: Giuseppe Rossini <giuseppe.rossini@arm.com>
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: Ib4ca28b82bd82f0ed4d2c906185d3f4010246616
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/153986
Reviewed-by: Giuseppe Rossini <giuseppe.rossini@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: If3ca0b034a7448df1e5349b51a2b124f1b4e99c1
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/153956
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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COMPMID-1651: Fix QASYMM8 CLDeconvolutionLayer
This patch also extends the range of values used for testing Convolution and
Deconvolution to cover quantized [-1.0f, 1.0f].
Change-Id: I8b280669db67bb3ec25bf5d411c8f5954f5b0dab
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/149869
Reviewed-by: Michalis Spyrou <michalis.spyrou@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: Id331199f569f52a37280a9ada5bf84694580b93c
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/152843
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
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(384496)
Mirroring CLGEMM behaviour to CLGEMMLowp
Change-Id: I308b54e2c0de131a5322b77e83e7454db498d692
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/153175
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: Ida71312bcf6dbd854f2ab1efc65f74910c79e152
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/151510
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
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Change-Id: I9dd26b80025ea3a4c66f5f0bf41b7a98dd0d3aa4
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/152549
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
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Change-Id: Ic857b938130c3d8713c9b414249cfabdcf846c2b
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/152451
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Vidhya Sudhan Loganathan <vidhyasudhan.loganathan@arm.com>
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Change-Id: I5f2e6843526cb154176a5b113627d4f36c3a8edd
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/150967
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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instrumentation timer is enabled
issue description: cpu info was neither initialised in scheduler timer interceptor nor was it retrieved from real scheduler.
Change-Id: Ibe75b0704250d99682ed866deaf3ddf5fda22de5
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/151451
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Current implementation of winograd fp16 is not accurate enough for large runs.
disabling its use and reopening ticket(COMPMID-1266) to fix it.
The sigbus error that was originally reported against COMPMID-1559 is being tracked as COMPMID-1606
Change-Id: I45129aa366d5710402bc54b623c5fbfb865b3cd5
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/151543
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
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Change-Id: Ie215daacd10477309dbf8af1bb2b05b7a0a8f203
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/150773
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
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