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* Datatype supported qasymm8 and qasymm8_signed.
* Resolves COMPMID-5211
Change-Id: Ib161af3af5ad11ec6b46de0bf4fbac172d2525fb
Signed-off-by: Pablo Marquez Tello <pablo.tello@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7729
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
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The new version introduces the following major changes:
* Change public interface to simplify and standardize the user experience
- Use the term "Workload" uniformly
- Simplify operator interface to be a set of static methods:
validate_op(), create_op()
* Separate the kernel writing into its own component (template_writer).
This is to allow the co-development of GpuKernelWriter, and to allow
easy replacement once GpuKernelWriter is mature.
* Optimize the core fusion algorithm used by the component graph. The
details can be found in GpuKernelComponentGraph::fuse()
* Use Gpu instead of Cl prefixes for most of the Workload interfaces
(except for runtime and kernel components, which have to be language specific)
This allows the potential extension to other Gpu langauges in the
future.
* Refactor runtime memory interface so that auxiliary tensor handling
is separate from the user tensor passing. This is because the former
is less stable and may require extension in the future.
* Hide source code object from the user as it is not required at the
moment
* Deprecate the old prototype entirely by disabling it in SCons build
Resolves COMPMID-5510, COMPMID-5512, COMPMID-5513
Change-Id: If69d2362856f2de4503546b7b6cf48a525cf3079
Signed-off-by: SiCong Li <sicong.li@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8406
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Reviewed-by: Jakub Sujak <jakub.sujak@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
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This patch introduces several performance optimizations regarding the Bilinear Scale operator with REPLICATE Border mode. Changes apply only to NHWC.
This patch
- Reduces the memory footprint by disabling precomputation of indices and weights when they're not used
- Rewrites the kernels for QASYMM8/QASYMM8_SIGNED/U8(Uint8)
- Adds S8(Int8) Bilinear Scale for Border mode REPLICATE
- Removes Bilinear Scale SVE kernels for Quantized and Integer types and adjust the heuristics to choose the Neon™ implementation
- Adds new test cases where the input and output of the Bilinear Scale operator have different quantization scale and offset
Resolves: COMPMID-5453, COMPMID-5454
Change-Id: I3d251e76e0c6978fd5a0a1795ec62ab536bec93c
Signed-off-by: Gunes Bayir <gunes.bayir@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8250
Reviewed-by: SiCong Li <sicong.li@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
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Implements LayerNorm for qasymm8 tensors.
Uses uint8x16 loads and stores.
Summation is performed in integer arithmetic (vpaddl)
Normalization is performed in float32 before requantizing back to int8.
Signed-off-by: Murray Kornelsen <murray.kornelsen@mail.mcgill.ca>
Change-Id: I2407c8b34717fb47adab98791bd76fb8a3c62f4a
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7922
Comments-Addressed: Pablo Marquez Tello <pablo.tello@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
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* Move LUT implementation to a seperate file. It will be used
for both QASYMM8 and QASYMM8_SIGNED.
* Fix wrong constant value related to QASYMM8_SIGNED leaky ReLU
in 32-bit build.
Resolves: COMPMID-5464
Signed-off-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Change-Id: I2b24d52409a38f1b66fd532f431eff8a9e4547b6
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/8066
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
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This patch introduces a GEMMLowp routine that is optimized for Arm(R) Mali(TM)-G715 and Arm(R) Mali(TM)-G615
Resolves: COMPMID-5398
Signed-off-by: Freddie Liardet <frederick.liardet@arm.com>
Signed-off-by: Gunes Bayir <gunes.bayir@arm.com>
Change-Id: I8d06453645688f3658b6c7c06f1ebc25a2505661
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7932
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: SiCong Li <sicong.li@arm.com>
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
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Partially Resolves: COMPMID-5400
Signed-off-by: Ramy Elgammal <ramy.elgammal@arm.com>
Change-Id: I9ed6b85b105a15b1a35c6a921f63ea94c665438b
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/c/VisualCompute/ComputeLibrary/+/437221
Tested-by: bsgcomp <bsgcomp@arm.com>
Comments-Addressed: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7933
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
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Resolves: COMPMID-5400
Signed-off-by: Ramy Elgammal <ramy.elgammal@arm.com>
Change-Id: Ib4428436dd7a6e40d8b2d8a2f8dac1b079154551
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7894
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
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This patch introduces a GEMM routine that is optimized for Arm(R) Mali(TM)-G715 and Arm(R) Mali(TM)-G615
Resolves: COMPMID-5216
Signed-off-by: Gunes Bayir <gunes.bayir@arm.com>
Change-Id: I2e5d7806f5904347185bb3e250f73d73d6669dba
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7914
Reviewed-by: SiCong Li <sicong.li@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
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Resolves COMPMID-5298
Change-Id: Ie9b907e5dcf86aa6add8d08799fa7ba7c264edea
Signed-off-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7888
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: SiCong Li <sicong.li@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
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Resolves: COMPMID-5355
Change-Id: I92f73fbe885f28bbe7b07965b90cfd807c93602f
Signed-off-by: Michalis Spyrou <michalis.spyrou@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7745
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: SiCong Li <sicong.li@arm.com>
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This is a No Functional Change Intended (NFCI) patch. It imports the
kernel in the code, but the interface to select them and expose the
format of the weight tensors to the user will be provided in a
subsequent patch.
Kernels and kernel selection code in arm_gemm has been provided
by David.Mansell <David.Mansell@arm.com>.
The kernels are not compiled in the library by default, but need to be
selected via the `scons` option `experimental_fixed_format_kernels=1`.
Resolves: ONCPUML-829
Signed-off-by: Francesco.Petrogalli@arm.com <francesco.petrogalli@arm.com>
Change-Id: If00ccb2b9b7221e01b214cf9783111226ccc8bf4
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7380
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Reviewed-by: SiCong Li <sicong.li@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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* Add public interfaces:
* OperatorGraph: Describe a workload that could contain fused kernels
* IWorkload: Generic interface for workloads built from OperatorGraph
* ClWorkload: OpenCL workloads built from OperatorGraph
* ClCompositeOperator: Runtime async operator to execute a ClWorkload
* DependencyGraph (will likely be deprecated in later iterations)
* Add example
* cl_fused_conv2d_elementwise_add.cpp to explain how to use the new
interfaces
* Add internal translation layer
* Refactor ClKernelBuildingAPI
* Remove non-tile based gemm native kernel component
* Minor interface changes
* Add integration tests
Resolves COMPMID-5161
Signed-off-by: SiCong Li <sicong.li@arm.com>
Change-Id: Ib987ed79289ab0bcbd3130d54f5793408d9f1240
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7510
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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- Reduce duplication and simplify overall structure.
- Improve multi-threaded performance by sharing more data
in lower-level caches.
Partially Resolves: COMPMID-5054
Signed-off-by: Ramy Elgammal <ramy.elgammal@arm.com>
Change-Id: Iac747f39b21c540122fa75218762631c4d787911
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7449
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Andrew Mundy
Reviewed-by: Sheri Zhang <sheri.zhang@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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- Reduce duplication and simplify overall structure.
- Improve multi-threaded performance by sharing more data
in lower-level caches.
Partially Resolves: COMPMID-5054
Signed-off-by: Ramy Elgammal<ramy.elgammal@arm.com>
Change-Id: I5f4dc50913401d5c1cbfc10b866fae9490cbc4d7
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7404
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Andrew Mundy
Reviewed-by: Sheri Zhang <sheri.zhang@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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- Add implementation for the CPU pooling 3d layer.
- NDHWC data layout support.
- Support QASYMM8/QASYMM8_SIGNED.
- Add Pooling helper file for Pool3d/2d common functions.
Resolves COMPMID-4668
Change-Id: Iadf042036b076099c2353d6e2fe9fc623bc263d8
Signed-off-by: Adnan AlSinan <adnan.alsinan@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7387
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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Resolves: COMPMID-5156
Change-Id: I438da924cb80d3bce72106b06ca7181e0606bd01
Signed-off-by: Gunes Bayir <gunes.bayir@arm.com>
Signed-off-by: Giorgio Arena <giorgio.arena@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7399
Reviewed-by: SiCong Li <sicong.li@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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- Add implementation for the CPU pooling 3d layer.
- NDHWC data layout support
- Support FP32/FP16.
- Add Pool3d to the operator list.
- Fix CL Pool3d kernel comments to generate the operator list.
Resolves: COMPMID-4671
Signed-off-by: Adnan AlSinan <adnan.alsinan@arm.com>
Change-Id: I92478a154beb12541525b648ed3dd5a58c8f27fa
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7311
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
(cherry picked from commit 572659a0e5dd1086b1c7d16fe331ff73d2acd93a)
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- For NDHWC layout
- For F16 and F32 data types
- Mixed Precision stil not supported
Resolves: COMPMID-4670
Signed-off-by: ramy.elgammal@arm.com
Change-Id: I0e14a13e4625569e8e5ee67e6033bd1efe0da469
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7262
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: SiCong Li <sicong.li@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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- Decouple data type for CPU implementation
supported data types are: fp32, fp16
Resolves COMPMID-4613
Signed-off-by: Yair Schwarzbaum <yair.schwarzbaum@arm.com>
Change-Id: I8aff3ba2d446f64e4d182a866e3a3debc9ef613b
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7175
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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Resolves: COMPMID-5151
Signed-off-by: Giorgio Arena <giorgio.arena@arm.com>
Change-Id: Ic4024d5cd4819fe917a1d49621f1866ae2e90a37
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7260
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: SiCong Li <sicong.li@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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Resolves: COMPMID-4625
Signed-off-by: Yair Schwarzbaum <yair.schwarzbaum@arm.com>
Change-Id: I3c30f007804b179e5e2b439f421fbd4e57fb02e1
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7149
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
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* Update json struct meet multi-ISA updates
* Add impl.cpp in kernels where we only have impl.h
Resolves COMPMID-5173
Change-Id: I5da3c4b016a5d0115c4ba46cbfefde7bce518ac1
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7191
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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Resolves COMPMID-4626
Exclude SVE & SVE2 paths from android.bp
NDK version does not support these extensions.
Change-Id: I49b147d2a84819975d3225f2920106fa1a0d742f
Signed-off-by: alerah01 <alex.rahlis@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7136
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
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Resolves COMPMID-4632
Change-Id: I5e2a9f0f7801a2afaa35de871ab29cd7238923fd
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7115
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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Resolves: COMPMID-4615
Signed-off-by: Yair Schwarzbaum <yair.schwarzbaum@arm.com>
Change-Id: Iadbfb3e45831a5072962b5b9f61e8ae2e674ccc4
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7016
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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Resolves COMPMID-4629, COMPMID-4631
Change-Id: Idceafc84735116ef63ec13a202895f954b87e32f
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7095
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: SiCong Li <sicong.li@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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Resolves COMPMID-4958
Change-Id: Ibed5155f2e3ece46635f6ea9617bf11cefc402b1
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7028
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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* Softmax kernel
* Elementwise unary kernel
* Elementwise binary
** This change require some refactor in the kernel cpp and h files
Resolves COMPMID-5043
Change-Id: I58979b023ec31d759690847b3f85fc4baefbbf98
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7033
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
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- Remove CLRemapKernel.
- Remove NERemapKernel.
Partially resolves COMPMID-4984
Signed-off-by: Adnan AlSinan <adnan.alsinan@arm.com>
Change-Id: Ia61f9ac7447695d81178701cf0e9b7625a91eccc
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7056
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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* Add kernel selection at build time
* Modify filelist.json to allow files separation
as part of our kernel decoupling process.
Issues to address after this change will be merged:
(1) Remove SVE/SVE2 defines from already decoupled kernels
(2) Adapt the new file list structure (filelist.json)
resolves COMPMID-4996 and COMPMID-5048
Change-Id: I8c17a9d6b150bbc7d8c1f2ed38060be82b6aa904
Signed-off-by: Motti Gondabi <motti.gondabi@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7006
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: SiCong Li <sicong.li@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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Resolves COMPMID-4614
Signed-off-by: Anton Vainer <anton.vainer@arm.com>
Change-Id: I19476d43b8e685de2eed973425d5d31b9cdb84ca
Signed-off-by: Anton Vainer <anton.vainer@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6960
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
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1- reorganize the folders struct according the new definition
2- separate between unary and binary implementations
3- decuple kernels - unary , binary op and binary comparision
Resolves COMPMID-4634
Change-Id: I0195846cc372e74a63c659069a4508de53a22110
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6860
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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Resolves COMPMID-4633
Change-Id: I9f93b28fbc3b18ccaeb453596dc8e0eddfe06b6a
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6861
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Pablo Marquez Tello <pablo.tello@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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Resolves COMPMID-4617
Change-Id: Ic8793aaf64c6137f848f39c62e33b44ae79ad21d
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6870
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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Resolves COMPMID-4620
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Change-Id: I22c285339840493c9cfd4c1abfbc3768ad4db824
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6871
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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Resolves COMPMID-4622
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Change-Id: I18acd03e323f7734635284a763442d2cb4ded177
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6872
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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Resolves COMPMID-4624
Change-Id: Ib8d24c44ae62c4f8272310c9305d863d8447eafa
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6873
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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Resolves COMPMID-4621
Change-Id: I3d89fa6d8273cc5f61a5cc0470fd730919bcd432
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/c/VisualCompute/ComputeLibrary/+/385363
Tested-by: bsgcomp <bsgcomp@arm.com>
Comments-Addressed: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6867
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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Resolves COMPMID-4619
Change-Id: I9c43dcd3fb3a688e1c0ccc858a02376741381ba7
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6874
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
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Change-Id: I1f39ba6a255847f4d21837a3dce4f867322203e6
Signed-off-by: alerah01 <alex.rahlis@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6799
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
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1- Data types were already decoupled. This commit arrange the folder struct of the activation kernel.
2- Refactor NEON CpuActivationKernel for floating-point cases.
Resolves COMPMID-4636
Change-Id: Ia4527244c84260dce1dd1d4bd4a9e3cfe2486d85
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6739
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
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Resolves: COMPMID-4910
Signed-off-by: Ramy Elgammal <ramy.elgammal@arm.com>
Change-Id: I79b4aa51e07ad1fe81d9218ed8a8f34f0ec5ab06
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6803
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Sheri Zhang <sheri.zhang@arm.com>
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1- NEON supported data types are : fp32, fp16, u8, s16, s32 , q8, q_s8 , q16
2- SVE supported data types are: fp32, fp16, u8, s16, s32
3- SVE2 supported data types are : q8, q_s8 , q16
4- Re-arange SVE folder sturct
** Need to remove gaurds and add testing after Multi ISA build system and validation tests will be avalible
Resolves COMPMID-4635
Change-Id: I90e4f6a219478aa9ad5c4a6b9858496afa8af42d
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6711
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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- Decouple data type for CPU implementation,
supported data types are: fp32, fp16, u8, u16, u32, s8, s16, s32
Resolves COMPMID-4612
Signed-off-by: Yair Schwarzbaum <yair.schwarzbaum@arm.com>
Change-Id: Iec9aab9f59c5a344950c788281fc500290a19bbc
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6686
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
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Resolves: COMPMID-4972
Signed-off-by: Freddie Liardet <frederick.liardet@arm.com>
Change-Id: Iaf9e709beafcfc58c4c1b04912e363cd287f07cf
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6659
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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Resolves: COMPMID-4866
Signed-off-by: Freddie Liardet <frederick.liardet@arm.com>
Change-Id: Id03ce0f5c25e0c0cef92ef9686201d96963fd7c1
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6464
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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Resolves COMPMID-4446
Change-Id: I1d3c2391b67681f4d3af440826aa95b47a1288a6
Signed-off-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6444
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
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Allow ACL to be built via a user provided JSON file containing operators, data types and data layouts.
Modify TFLite file to JSON file script to output data layouts.
Fix build issue with "fat_binary" and "high_priority" options.
Resolves: COMPMID-4697, COMPMID-4837
Signed-off-by: Freddie Liardet <frederick.liardet@arm.com>
Change-Id: I08d494151c98f804325707ffd922ffe216813023
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6427
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Gunes Bayir <gunes.bayir@arm.com>
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* Add CpuDirectConv3d support for fp32 and fp16
* Dilation is not supported
* Need decouple
Partially resolve: COMPMID-4661
Signed-off-by: Sheri Zhang <sheri.zhang@arm.com>
Change-Id: Ib1865b9ff328b684d131512b1baf77bc2f10318f
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6430
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
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