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NEWidthConcatenateLayerKernel works with 4D tensors too, hence the check has
been removed and tests have been added.
Change-Id: I73814cabe5fae975a44cc1a03b092c552497e57d
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155070
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
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Change-Id: I7bd4a8ce81483ba56686b765ca3caabebe42882d
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155000
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
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vector
When one of the operands is a vector, the kernel does a broadcast addition and
the window is not collapsed. This represent an issue because it leads to a lot
of enqueues that increases the time taken by the OpenCL driver. This patch
allows to collapse the window when one of the two operands is a vector.
Furthermore, it adds LWS tuner to the kernel.
It also changes the number of elements processed per iteration to 8 to make
better usage of the cache.
Change-Id: I5f09ab0ddcffb3b7f9326a987c79a997b2d7fa8c
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/155003
Reviewed-by: Giuseppe Rossini <giuseppe.rossini@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: Id106d53b9477298a117a5195f3fc5b0f36003c35
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/131903
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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Change-Id: Ic8312a5b6790aa7cd4468d42f08d557ad40e9441
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154570
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
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Change-Id: Id964d9068e18aaa13ab8adcbf7a9375b034ea6c3
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154651
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
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Change-Id: I91865506166951b3bf7f06a0b2d4cde925cfefb6
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/153447
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
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NEGEMMConvolutionLayer.
Change-Id: Iea5f2c5bcac8051c4c7655a6eabb2c43772eb31f
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154104
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
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Change-Id: Iae22554d5fe893fd22a000eab5bfd8275ea06eb3
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154102
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: I146936c9e98b343496a4b61cdbadf0eaa38e885a
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154008
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
Reviewed-by: Giuseppe Rossini <giuseppe.rossini@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: Ibc0b1242804c2fdb183825406e3c78bd0d1d3564
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154368
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: Id974efad304c2513b8824a6561ad45ee60b9e7fb
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/153763
Reviewed-by: Giuseppe Rossini <giuseppe.rossini@arm.com>
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: Ib4ca28b82bd82f0ed4d2c906185d3f4010246616
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/153986
Reviewed-by: Giuseppe Rossini <giuseppe.rossini@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Enabled NHWC as default data layout in AlexNet, InceptionV3 and InceptionV4 on NEON
Change-Id: I205ad7a1f5dbf482340182de4fac8f3a24ef2705
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154141
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: If496709958bf29589601eac62a268819736a4fd2
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/154173
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: If3ca0b034a7448df1e5349b51a2b124f1b4e99c1
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/153956
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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COMPMID-1651: Fix QASYMM8 CLDeconvolutionLayer
This patch also extends the range of values used for testing Convolution and
Deconvolution to cover quantized [-1.0f, 1.0f].
Change-Id: I8b280669db67bb3ec25bf5d411c8f5954f5b0dab
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/149869
Reviewed-by: Michalis Spyrou <michalis.spyrou@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: Id331199f569f52a37280a9ada5bf84694580b93c
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/152843
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
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Change-Id: I05a1b871746a32ccc1c3ecec97b8266767c9d0a7
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/153715
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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(384496)
Mirroring CLGEMM behaviour to CLGEMMLowp
Change-Id: I308b54e2c0de131a5322b77e83e7454db498d692
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/153175
Reviewed-by: Gian Marco Iodice <gianmarco.iodice@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: I2c4dcedcd3b56e41174eebbbacd47be4e968d34d
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/152767
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Vidhya Sudhan Loganathan <vidhyasudhan.loganathan@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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NEON and CL normalization layer was generating invalida results for
radius > 4.
Change-Id: I15d846405e6b3492fe44920bbf8cadceb4e5258f
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/153161
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Matteo Martincigh <matteo.martincigh@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
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Change-Id: Ida71312bcf6dbd854f2ab1efc65f74910c79e152
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/151510
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
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Change-Id: I05d3447336ee0bf330e2a0c58fc6904be1db8f83
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/152626
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
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Since this is floating point arithmetic the Winograd results will not be exactly
the same as direct convolution.
Changed to use relative tolerance for the nightly tests.
Change-Id: I45c6d60a097c2d4fb53650a2a33eb29a3e51d7ec
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/152324
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
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Change-Id: I4d9240924fe483d2dd127ad6a4ae6f8066f61bd1
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/151893
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Andrew Mundy <andrew.mundy@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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call to print_cpu_info moved to main
Change-Id: I6d82649964542df4e944bc79e4c16f0813976295
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/152695
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
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Change-Id: I9dd26b80025ea3a4c66f5f0bf41b7a98dd0d3aa4
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/152549
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
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Change-Id: Ic857b938130c3d8713c9b414249cfabdcf846c2b
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/152451
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Vidhya Sudhan Loganathan <vidhyasudhan.loganathan@arm.com>
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conditionally compile the std::cout that was causing the fault
Change-Id: I7f50151ab88f19ed6eec1be11ca975614653e359
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/151762
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: I5f2e6843526cb154176a5b113627d4f36c3a8edd
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/150967
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: I062e7673f26d5267ed113eae7edd361d05d6de73
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/151968
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: I4920e43059a713126f15493f38fe50f07d0a8c7f
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/151087
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
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Kernel size 5x5 layout NHWC.
Change-Id: Ia82ff211d1c954df228962b5c2c5ad8df7112449
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/151740
Reviewed-by: Michalis Spyrou <michalis.spyrou@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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instrumentation timer is enabled
issue description: cpu info was neither initialised in scheduler timer interceptor nor was it retrieved from real scheduler.
Change-Id: Ibe75b0704250d99682ed866deaf3ddf5fda22de5
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/151451
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Current implementation of winograd fp16 is not accurate enough for large runs.
disabling its use and reopening ticket(COMPMID-1266) to fix it.
The sigbus error that was originally reported against COMPMID-1559 is being tracked as COMPMID-1606
Change-Id: I45129aa366d5710402bc54b623c5fbfb865b3cd5
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/151543
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
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Change-Id: Ie215daacd10477309dbf8af1bb2b05b7a0a8f203
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/150773
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
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Change-Id: I6f71f2da851454e8fbbdfc9223592dea9ad03bac
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/151014
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Giuseppe Rossini <giuseppe.rossini@arm.com>
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
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COMPMID-1608 - (Nightly) CLGEMMConvolutionLayer QASYMM8 errors and mismatches
COMPMID-1609 - (Nightly) CLFullyConnectedLayer QASYMM8 mismatches
Change-Id: I84c0d4f468be892f437f9f38b964dc7dfb66663a
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/150869
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: I62bbf510cc106a90ed2884be3c9c0c127da25898
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/150681
Reviewed-by: Giuseppe Rossini <giuseppe.rossini@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: I1778a76f6c225da7e2c07b39fdf6c3894624701b
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/149933
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Fixing bounds of random values for Normalize Planar YUV tests when using
QASYMM8.
Furthermore, since 70d252d8b4 a QASYMM8 implementation of Batch Normalization
would have been tested with tensors filled with all 1s. This patch removes that
as QASYMM8 Batch Normalization is not supported.
Change-Id: Ieab83ed36b2d7af760ceb19a07d1eedcc991957f
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/150492
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: I637add70310d2da4d82b236a6352af9d33be17a1
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/149706
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: I4d06eca9404ea6d3df9d0ca52f5d6f5421ab7116
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/150117
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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Change-Id: I47033fa70881fd32b13266adb6ccbf10c202aabc
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/150344
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
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Change-Id: I82d95c4f1c5fed13b213a2591cc2b4e0d0e02a54
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/149676
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Reviewed-by: Pablo Tello <pablo.tello@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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Change-Id: Ib14ac821ee5d4aff80bd602cd3e76e7018abb5e6
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/150268
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
Reviewed-by: Michele DiGiorgio <michele.digiorgio@arm.com>
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Change-Id: I9250b2e8020fe87c6ed4de582bbc7460bbd8e94b
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/150287
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Isabella Gottardi <isabella.gottardi@arm.com>
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Change-Id: Ic985ac8b0b09c3a6b3f2d43274af8ce89f8c90dd
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/150313
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Tested-by: bsgcomp <bsgcomp@arm.com>
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RSH code only support padding SAME|VALID, this means we cannot
call it with padx=1 for kernel size 5x5. The supporting padding
values are 2 and 0.
Fixed the problem by modifying the test shapes and added some
asserts in NEWinogradConvolutionLayer.
Change-Id: I4b73fa9d13c2200a47002965dc3b471d0f2cafba
Reviewed-on: https://eu-gerrit-1.euhpc.arm.com/149883
Tested-by: bsgcomp <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
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