diff options
Diffstat (limited to 'src/cpu/kernels/CpuAddKernel.cpp')
| -rw-r--r-- | src/cpu/kernels/CpuAddKernel.cpp | 102 |
1 files changed, 19 insertions, 83 deletions
diff --git a/src/cpu/kernels/CpuAddKernel.cpp b/src/cpu/kernels/CpuAddKernel.cpp index 47ff6abf17..1648a46cdc 100644 --- a/src/cpu/kernels/CpuAddKernel.cpp +++ b/src/cpu/kernels/CpuAddKernel.cpp @@ -39,11 +39,6 @@ namespace cpu { namespace kernels { -bool can_interpret_inputs_as_1d_array(const ITensorInfo &src0, const ITensorInfo &src1) -{ - return !src0.has_padding() && !src1.has_padding() && src0.tensor_shape() == src1.tensor_shape() && src0.strides_in_bytes() == src1.strides_in_bytes(); -} - namespace { static const std::vector<CpuAddKernel::AddKernel> available_kernels = @@ -65,50 +60,10 @@ static const std::vector<CpuAddKernel::AddKernel> available_kernels = REGISTER_FP32_NEON(arm_compute::cpu::add_q8_neon_fixedpoint<int8_t>) }, { - "neon_fp32_add_as_1d_array", - [](const CpuAddKernelDataTypeISASelectorData & data) - { - return (data.dt == DataType::F32) && data.can_interpret_inputs_as_1d_array == true; - }, - REGISTER_FP32_NEON(arm_compute::cpu::add_fp32_neon_as_1d_array) - }, - { - "neon_fp16_add_as_1d_array", - [](const CpuAddKernelDataTypeISASelectorData & data) - { - return (data.dt == DataType::F16) && data.can_interpret_inputs_as_1d_array == true; - }, - REGISTER_FP16_NEON(arm_compute::cpu::add_fp16_neon_as_1d_array) - }, - { - "neon_u8_add_as_1d_array", - [](const CpuAddKernelDataTypeISASelectorData & data) - { - return (data.dt == DataType::U8) && data.can_interpret_inputs_as_1d_array == true; - }, - REGISTER_INTEGER_NEON(arm_compute::cpu::add_u8_neon_as_1d_array) - }, - { - "neon_s16_add_as_1d_array", - [](const CpuAddKernelDataTypeISASelectorData & data) - { - return (data.dt == DataType::S16) && data.can_interpret_inputs_as_1d_array == true; - }, - REGISTER_INTEGER_NEON(arm_compute::cpu::add_s16_neon_as_1d_array) - }, - { - "neon_s32_add_as_1d_array", - [](const CpuAddKernelDataTypeISASelectorData & data) - { - return (data.dt == DataType::S32) && data.can_interpret_inputs_as_1d_array == true; - }, - REGISTER_INTEGER_NEON(arm_compute::cpu::add_s32_neon_as_1d_array) - }, - { "sve2_qu8_add", [](const CpuAddKernelDataTypeISASelectorData & data) { - return (data.dt == DataType::QASYMM8) && data.isa.sve2 && data.can_interpret_inputs_as_1d_array == false; + return (data.dt == DataType::QASYMM8) && data.isa.sve2; }, REGISTER_QASYMM8_SVE2(arm_compute::cpu::add_qasymm8_sve2) }, @@ -116,7 +71,7 @@ static const std::vector<CpuAddKernel::AddKernel> available_kernels = "sve2_qs8_add", [](const CpuAddKernelDataTypeISASelectorData & data) { - return (data.dt == DataType::QASYMM8_SIGNED) && data.isa.sve2 && data.can_interpret_inputs_as_1d_array == false; + return (data.dt == DataType::QASYMM8_SIGNED) && data.isa.sve2; }, REGISTER_QASYMM8_SIGNED_SVE2(arm_compute::cpu::add_qasymm8_signed_sve2) }, @@ -124,7 +79,7 @@ static const std::vector<CpuAddKernel::AddKernel> available_kernels = "sve2_qs16_add", [](const CpuAddKernelDataTypeISASelectorData & data) { - return (data.dt == DataType::QSYMM16) && data.isa.sve2 && data.can_interpret_inputs_as_1d_array == false; + return (data.dt == DataType::QSYMM16) && data.isa.sve2; }, REGISTER_QSYMM16_SVE2(arm_compute::cpu::add_qsymm16_sve2) }, @@ -132,7 +87,7 @@ static const std::vector<CpuAddKernel::AddKernel> available_kernels = "sve_fp32_add", [](const CpuAddKernelDataTypeISASelectorData & data) { - return (data.dt == DataType::F32) && data.isa.sve && data.can_interpret_inputs_as_1d_array == false; + return (data.dt == DataType::F32) && data.isa.sve; }, REGISTER_FP32_SVE(arm_compute::cpu::add_fp32_sve) }, @@ -140,7 +95,7 @@ static const std::vector<CpuAddKernel::AddKernel> available_kernels = "sve_fp16_add", [](const CpuAddKernelDataTypeISASelectorData & data) { - return (data.dt == DataType::F16) && data.isa.sve && data.isa.fp16 && data.can_interpret_inputs_as_1d_array == false; + return (data.dt == DataType::F16) && data.isa.sve && data.isa.fp16; }, REGISTER_FP16_SVE(arm_compute::cpu::add_fp16_sve) }, @@ -148,7 +103,7 @@ static const std::vector<CpuAddKernel::AddKernel> available_kernels = "sve_u8_add", [](const CpuAddKernelDataTypeISASelectorData & data) { - return (data.dt == DataType::U8) && data.isa.sve && data.can_interpret_inputs_as_1d_array == false; + return (data.dt == DataType::U8) && data.isa.sve; }, REGISTER_INTEGER_SVE(arm_compute::cpu::add_u8_sve) }, @@ -156,7 +111,7 @@ static const std::vector<CpuAddKernel::AddKernel> available_kernels = "sve_s16_add", [](const CpuAddKernelDataTypeISASelectorData & data) { - return (data.dt == DataType::S16) && data.isa.sve && data.can_interpret_inputs_as_1d_array == false; + return (data.dt == DataType::S16) && data.isa.sve; }, REGISTER_INTEGER_SVE(arm_compute::cpu::add_s16_sve) }, @@ -164,7 +119,7 @@ static const std::vector<CpuAddKernel::AddKernel> available_kernels = "sve_s32_add", [](const CpuAddKernelDataTypeISASelectorData & data) { - return (data.dt == DataType::S32) && data.isa.sve && data.can_interpret_inputs_as_1d_array == false; + return (data.dt == DataType::S32) && data.isa.sve; }, REGISTER_INTEGER_SVE(arm_compute::cpu::add_s32_sve) }, @@ -240,34 +195,11 @@ Status validate_arguments(const ITensorInfo &src0, const ITensorInfo &src1, cons const auto can_use_fixedpoint = add_q8_neon_fixedpoint_possible(&src0, &src1, &dst); const auto uk = CpuAddKernel::get_implementation<CpuAddKernelDataTypeISASelectorData>(CpuAddKernelDataTypeISASelectorData{ src0.data_type(), - CPUInfo::get().get_isa(), can_interpret_inputs_as_1d_array(src0, src1), can_use_fixedpoint }); + CPUInfo::get().get_isa(), can_use_fixedpoint }); ARM_COMPUTE_RETURN_ERROR_ON(uk == nullptr || uk->ukernel == nullptr); return Status{}; } - -std::pair<Status, Window> validate_and_configure_window(const ITensorInfo &src0, const ITensorInfo &src1, ITensorInfo &dst) -{ - if(can_interpret_inputs_as_1d_array(src0, src1)) - { - Window window; - window.set(0, Window::Dimension(0, src0.tensor_shape().total_size())); - return std::make_pair(Status{}, window); - } - else - { - const TensorShape &out_shape = TensorShape::broadcast_shape(src0.tensor_shape(), src1.tensor_shape()); - - // Auto initialize dst if not initialized - set_shape_if_empty(dst, out_shape); - set_data_type_if_unknown(dst, src0.data_type()); - - Window win = calculate_max_window(out_shape, Steps()); - - // CpuAddKernel doesn't need padding so update_window_and_padding() can be skipped - return std::make_pair(Status{}, win); - } -} } // namespace void CpuAddKernel::configure(const ITensorInfo *src0, const ITensorInfo *src1, ITensorInfo *dst, ConvertPolicy policy) @@ -275,10 +207,9 @@ void CpuAddKernel::configure(const ITensorInfo *src0, const ITensorInfo *src1, I ARM_COMPUTE_ERROR_ON_NULLPTR(src0, src1, dst); ARM_COMPUTE_ERROR_THROW_ON(validate_arguments(*src0, *src1, *dst, policy)); - _can_interpret_inputs_as_1d_array = can_interpret_inputs_as_1d_array(*src0, *src1); const auto can_use_fixedpoint = add_q8_neon_fixedpoint_possible(src0, src1, dst); const auto uk = CpuAddKernel::get_implementation<CpuAddKernelDataTypeISASelectorData>(CpuAddKernelDataTypeISASelectorData{ src0->data_type(), - CPUInfo::get().get_isa(), _can_interpret_inputs_as_1d_array, can_use_fixedpoint }); + CPUInfo::get().get_isa(), can_use_fixedpoint }); ARM_COMPUTE_ERROR_ON_NULLPTR(uk); @@ -286,10 +217,16 @@ void CpuAddKernel::configure(const ITensorInfo *src0, const ITensorInfo *src1, I _run_method = uk->ukernel; _name = std::string("CpuAddKernel").append("/").append(uk->name); + // Auto initialize dst if not initialized + const TensorShape &out_shape = TensorShape::broadcast_shape(src0->tensor_shape(), src1->tensor_shape()); + set_shape_if_empty(*dst, out_shape); + set_data_type_if_unknown(*dst, src0->data_type()); + // Configure kernel window - auto win_config = validate_and_configure_window(*src0, *src1, *dst); - ARM_COMPUTE_ERROR_THROW_ON(win_config.first); - ICpuKernel::configure(win_config.second); + Window win; + std::tie(win, _split_dimension) = calculate_squashed_or_max_window(*src0, *src1); + + ICpuKernel::configure(win); } Status CpuAddKernel::validate(const ITensorInfo *src0, const ITensorInfo *src1, const ITensorInfo *dst, ConvertPolicy policy) @@ -297,7 +234,6 @@ Status CpuAddKernel::validate(const ITensorInfo *src0, const ITensorInfo *src1, ARM_COMPUTE_RETURN_ERROR_ON_NULLPTR(src0, src1, dst); ARM_COMPUTE_RETURN_ON_ERROR(validate_arguments(*src0, *src1, *dst, policy)); - ARM_COMPUTE_RETURN_ON_ERROR(validate_and_configure_window(*src0->clone(), *src1->clone(), *dst->clone()).first); return Status{}; } |