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author | Freddie Liardet <frederick.liardet@arm.com> | 2021-05-04 12:41:16 +0100 |
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committer | frederick.liardet <frederick.liardet@arm.com> | 2021-05-13 13:13:06 +0000 |
commit | afcbb8f47427405a35be508425376286f0fd7a70 (patch) | |
tree | b373f2d2a6a94b53116c5a53da7c4b4181753486 /tests/datasets | |
parent | fd83bc8894007c2c9591896ba4229c99d8236a7a (diff) | |
download | ComputeLibrary-afcbb8f47427405a35be508425376286f0fd7a70.tar.gz |
Fix Pooling Layer Bug when input is 1xN size
Return error in pooling layer when any calculated output dimension is less than 1.
Simplify use of pooling layer output dimension values in
CpuPoolingKernel.cpp.
Remove some invalid tests in cpu/gpu pooling layers.
Resolves COMPMID-4358.
Signed-off-by: Freddie Liardet <frederick.liardet@arm.com>
Change-Id: If8f8ffec579d3eca1c27a45e5b0b684a77103cff
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5559
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'tests/datasets')
-rw-r--r-- | tests/datasets/PoolingLayerDataset.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/tests/datasets/PoolingLayerDataset.h b/tests/datasets/PoolingLayerDataset.h index 01b2491eb2..1557240fd2 100644 --- a/tests/datasets/PoolingLayerDataset.h +++ b/tests/datasets/PoolingLayerDataset.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020 Arm Limited. + * Copyright (c) 2017-2021 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -106,7 +106,7 @@ public: PoolingLayerDatasetSpecial() { // Special cases - add_config(TensorShape(2U, 3U, 4U, 1U), PoolingLayerInfo(PoolingType::AVG, Size2D(3, 3), DataLayout::NCHW, PadStrideInfo(3, 3, 0, 0), true)); + add_config(TensorShape(2U, 3U, 4U, 1U), PoolingLayerInfo(PoolingType::AVG, Size2D(2, 2), DataLayout::NCHW, PadStrideInfo(3, 3, 0, 0), true)); add_config(TensorShape(60U, 52U, 3U, 2U), PoolingLayerInfo(PoolingType::AVG, Size2D(100, 100), DataLayout::NCHW, PadStrideInfo(5, 5, 50, 50), true)); // Asymmetric padding add_config(TensorShape(112U, 112U, 32U), PoolingLayerInfo(PoolingType::MAX, 3, DataLayout::NCHW, PadStrideInfo(2, 2, 0, 1, 0, 1, DimensionRoundingType::FLOOR))); |