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author | Pablo Tello <pablo.tello@arm.com> | 2022-03-07 18:20:12 +0000 |
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committer | Pablo Marquez Tello <pablo.tello@arm.com> | 2022-03-10 13:44:39 +0000 |
commit | 4e66d707a292b90a344e32c59eb1dacb67a0e4c1 (patch) | |
tree | 48f8548c7a03f3586d27ae7b06d954b958912ee4 /src | |
parent | 17c48f9e518abfcb45477f0eeebf487498c6a270 (diff) | |
download | ComputeLibrary-4e66d707a292b90a344e32c59eb1dacb67a0e4c1.tar.gz |
Added windows native build support
Resolves MLCE-739
Signed-off-by: Pablo Tello <pablo.tello@arm.com>
Change-Id: I30a11393e928061c82a5c93d8ec195c04a0e838b
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/7279
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src')
-rw-r--r-- | src/common/cpuinfo/CpuInfo.cpp | 41 | ||||
-rw-r--r-- | src/core/NEON/kernels/arm_gemm/gemm_hybrid_indirect.hpp | 6 | ||||
-rw-r--r-- | src/core/NEON/kernels/arm_gemm/interleave_indirect.cpp | 6 | ||||
-rw-r--r-- | src/core/NEON/kernels/arm_gemm/transform.cpp | 6 | ||||
-rw-r--r-- | src/core/utils/misc/MMappedFile.cpp | 4 | ||||
-rw-r--r-- | src/core/utils/quantization/AsymmHelpers.cpp | 6 | ||||
-rw-r--r-- | src/cpu/CpuContext.cpp | 8 | ||||
-rw-r--r-- | src/runtime/BlobLifetimeManager.cpp | 3 | ||||
-rw-r--r-- | src/runtime/CPP/CPPScheduler.cpp | 4 |
9 files changed, 48 insertions, 36 deletions
diff --git a/src/common/cpuinfo/CpuInfo.cpp b/src/common/cpuinfo/CpuInfo.cpp index 2b85375654..0be21be085 100644 --- a/src/common/cpuinfo/CpuInfo.cpp +++ b/src/common/cpuinfo/CpuInfo.cpp @@ -34,18 +34,23 @@ #include <algorithm> #include <cstring> #include <fstream> +#if !defined(_WIN64) #include <regex.h> /* C++ std::regex takes up a lot of space in the standalone builds */ #include <sched.h> +#endif /* !defined(_WIN64) */ + #include <thread> #include <unordered_map> #endif /* !defined(BARE_METAL) */ +#if !defined(_WIN64) #if !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) #include <asm/hwcap.h> /* Get HWCAP bits from asm/hwcap.h */ #include <sys/auxv.h> #elif defined(__APPLE__) && defined(__aarch64__) #include <sys/sysctl.h> #include <sys/types.h> +#endif /* defined(__APPLE__) && defined(__aarch64__)) */ #endif /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */ #define ARM_COMPUTE_CPU_FEATURE_HWCAP_CPUID (1 << 11) @@ -57,7 +62,7 @@ namespace cpuinfo { namespace { -#if !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) +#if !defined(_WIN64) && !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) /** Extract MIDR using CPUID information that are exposed to user-space * * @param[in] max_num_cpus Maximum number of possible CPUs @@ -261,19 +266,19 @@ int get_max_cpus() } return max_cpus; } -#elif defined(__aarch64__) && defined(__APPLE__) /* !defined(BARE_METAL) && !defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__)) */ +#elif defined(__aarch64__) && defined(__APPLE__) /* !defined(BARE_METAL) && !defined(__APPLE__) && (defined(__arm__) || defined(__aarch64__)) */ /** Query features through sysctlbyname * * @return int value queried */ -int get_hw_capability(const std::string& cap) +int get_hw_capability(const std::string &cap) { - int64_t result(0); - size_t size = sizeof(result); - sysctlbyname(cap.c_str(), &result, &size, NULL, 0); - return result; + int64_t result(0); + size_t size = sizeof(result); + sysctlbyname(cap.c_str(), &result, &size, NULL, 0); + return result; } -#endif /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */ +#endif /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */ #if defined(BARE_METAL) && defined(__aarch64__) uint64_t get_sve_feature_reg() @@ -297,7 +302,7 @@ CpuInfo::CpuInfo(CpuIsaInfo isa, std::vector<CpuModel> cpus) CpuInfo CpuInfo::build() { -#if !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) +#if !defined(_WIN64) && !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) const uint32_t hwcaps = getauxval(AT_HWCAP); const uint32_t hwcaps2 = getauxval(AT_HWCAP2); const uint32_t max_cpus = get_max_cpus(); @@ -328,7 +333,7 @@ CpuInfo CpuInfo::build() CpuInfo info(isa, cpus_model); return info; -#elif(BARE_METAL) && defined(__aarch64__) /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */ +#elif(BARE_METAL) && defined(__aarch64__) /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */ // Assume single CPU in bare metal mode. Just read the ID register and feature bits directly. uint64_t isar0 = 0, isar1 = 0, pfr0 = 0, svefr0 = 0, midr = 0; @@ -346,18 +351,18 @@ CpuInfo CpuInfo::build() CpuInfo info(isa, cpus_model); return info; #elif defined(__aarch64__) && defined(__APPLE__) /* #elif(BARE_METAL) && defined(__aarch64__) */ - int ncpus = get_hw_capability("hw.logicalcpu"); - CpuIsaInfo isainfo; + int ncpus = get_hw_capability("hw.logicalcpu"); + CpuIsaInfo isainfo; std::vector<CpuModel> cpus_model(ncpus); isainfo.neon = get_hw_capability("hw.optional.neon"); isainfo.fp16 = get_hw_capability("hw.optional.neon_fp16"); - isainfo.dot = get_hw_capability("hw.optional.arm.FEAT_DotProd"); - CpuInfo info(isainfo,cpus_model); + isainfo.dot = get_hw_capability("hw.optional.arm.FEAT_DotProd"); + CpuInfo info(isainfo, cpus_model); return info; -#else /* #elif defined(__aarch64__) && defined(__APPLE__) */ +#else /* #elif defined(__aarch64__) && defined(__APPLE__) */ CpuInfo info(CpuIsaInfo(), { CpuModel::GENERIC }); return info; -#endif /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */ +#endif /* !defined(BARE_METAL) && !defined(__APPLE__) && !defined(__OpenBSD__) && (defined(__arm__) || defined(__aarch64__)) */ } CpuModel CpuInfo::cpu_model(uint32_t cpuid) const @@ -371,7 +376,7 @@ CpuModel CpuInfo::cpu_model(uint32_t cpuid) const CpuModel CpuInfo::cpu_model() const { -#if defined(BARE_METAL) || defined(__APPLE__) || defined(__OpenBSD__) || (!defined(__arm__) && !defined(__aarch64__)) +#if defined(_WIN64) || defined(BARE_METAL) || defined(__APPLE__) || defined(__OpenBSD__) || (!defined(__arm__) && !defined(__aarch64__)) return cpu_model(0); #else /* defined(BARE_METAL) || defined(__APPLE__) || defined(__OpenBSD__) || (!defined(__arm__) && !defined(__aarch64__)) */ return cpu_model(sched_getcpu()); @@ -387,7 +392,7 @@ uint32_t num_threads_hint() { unsigned int num_threads_hint = 1; -#if !defined(BARE_METAL) +#if !defined(BARE_METAL) && !defined(_WIN64) std::vector<std::string> cpus; cpus.reserve(64); diff --git a/src/core/NEON/kernels/arm_gemm/gemm_hybrid_indirect.hpp b/src/core/NEON/kernels/arm_gemm/gemm_hybrid_indirect.hpp index 79fc65e561..5b3ef4203d 100644 --- a/src/core/NEON/kernels/arm_gemm/gemm_hybrid_indirect.hpp +++ b/src/core/NEON/kernels/arm_gemm/gemm_hybrid_indirect.hpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021 Arm Limited. + * Copyright (c) 2017-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -23,9 +23,9 @@ */ #pragma once -#if !defined(__OpenBSD__) +#if !defined(_WIN64) && !defined(__OpenBSD__) #include <alloca.h> -#endif /* !defined(__OpenBSD__) */ +#endif /* !defined(_WIN64) && !defined(__OpenBSD__) */ #include <algorithm> #include <cassert> diff --git a/src/core/NEON/kernels/arm_gemm/interleave_indirect.cpp b/src/core/NEON/kernels/arm_gemm/interleave_indirect.cpp index 91988e8c33..59591935cd 100644 --- a/src/core/NEON/kernels/arm_gemm/interleave_indirect.cpp +++ b/src/core/NEON/kernels/arm_gemm/interleave_indirect.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2020-2021 Arm Limited. + * Copyright (c) 2020-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -28,9 +28,9 @@ #include "interleave_indirect.hpp" #include "bfloat.hpp" -#if !defined(__OpenBSD__) +#if !defined(_WIN64) && !defined(__OpenBSD__) #include <alloca.h> -#endif /* !defined(__OpenBSD__) */ +#endif /* !defined(_WIN64) && !defined(__OpenBSD__) */ #include <algorithm> #include <cstddef> diff --git a/src/core/NEON/kernels/arm_gemm/transform.cpp b/src/core/NEON/kernels/arm_gemm/transform.cpp index c6a3bc0edb..ef5a01a578 100644 --- a/src/core/NEON/kernels/arm_gemm/transform.cpp +++ b/src/core/NEON/kernels/arm_gemm/transform.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -25,9 +25,9 @@ #include "bfloat.hpp" -#if !defined(__OpenBSD__) +#if !defined(_WIN64) && !defined(__OpenBSD__) #include <alloca.h> -#endif /* !defined(__OpenBSD__) */ +#endif /* !defined(_WIN64) && !defined(__OpenBSD__) */ namespace arm_gemm { diff --git a/src/core/utils/misc/MMappedFile.cpp b/src/core/utils/misc/MMappedFile.cpp index 0b9414107e..adae8a2bf0 100644 --- a/src/core/utils/misc/MMappedFile.cpp +++ b/src/core/utils/misc/MMappedFile.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2019 Arm Limited. + * Copyright (c) 2019, 2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -21,7 +21,7 @@ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ -#if !defined(BARE_METAL) +#if !defined(_WIN64) && !defined(BARE_METAL) #include "arm_compute/core/utils/misc/MMappedFile.h" diff --git a/src/core/utils/quantization/AsymmHelpers.cpp b/src/core/utils/quantization/AsymmHelpers.cpp index 4ce60996f5..eb008639b1 100644 --- a/src/core/utils/quantization/AsymmHelpers.cpp +++ b/src/core/utils/quantization/AsymmHelpers.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2021 Arm Limited. + * Copyright (c) 2017-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -206,7 +206,9 @@ int32_t saturating_rounding_doubling_highmul(int32_t a, int32_t b) int64_t a_64(a); int64_t b_64(b); int64_t ab_64 = a_64 * b_64; - bool is_positive_or_zero = a == 0 || b == 0 || (std::signbit(a) == std::signbit(b)); + const bool is_positive_or_zero = + a == 0 || b == 0 || + (std::signbit(static_cast<double>(a)) == std::signbit(static_cast<double>(b))); int32_t nudge = is_positive_or_zero ? (1 << 30) : (1 - (1 << 30)); int32_t ab_x2_high32 = static_cast<int32_t>((ab_64 + nudge) / (1ll << 31)); return overflow ? std::numeric_limits<int32_t>::max() : ab_x2_high32; diff --git a/src/cpu/CpuContext.cpp b/src/cpu/CpuContext.cpp index 0cc5070917..d91f917963 100644 --- a/src/cpu/CpuContext.cpp +++ b/src/cpu/CpuContext.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021 Arm Limited. + * Copyright (c) 2021-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -30,8 +30,12 @@ #include <cstdlib> #if !defined(__APPLE__) && !defined(__OpenBSD__) #include <malloc.h> -#endif // !defined(__APPLE__) && !defined(__OpenBSD__) +#if defined(_WIN64) +#define posix_memalign _aligned_realloc +#define posix_memalign_free _aligned_free +#endif // defined(_WIN64) +#endif // !defined(__APPLE__) && !defined(__OpenBSD__) namespace arm_compute { diff --git a/src/runtime/BlobLifetimeManager.cpp b/src/runtime/BlobLifetimeManager.cpp index 1c983aa329..bea55d8eb9 100644 --- a/src/runtime/BlobLifetimeManager.cpp +++ b/src/runtime/BlobLifetimeManager.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2017-2020 Arm Limited. + * Copyright (c) 2017-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -30,6 +30,7 @@ #include <algorithm> #include <cmath> +#include <iterator> #include <map> namespace arm_compute diff --git a/src/runtime/CPP/CPPScheduler.cpp b/src/runtime/CPP/CPPScheduler.cpp index 94a2f31d64..39811ec156 100644 --- a/src/runtime/CPP/CPPScheduler.cpp +++ b/src/runtime/CPP/CPPScheduler.cpp @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2021 Arm Limited. + * Copyright (c) 2016-2022 Arm Limited. * * SPDX-License-Identifier: MIT * @@ -104,7 +104,7 @@ void set_thread_affinity(int core_id) return; } -#if !defined(__APPLE__) && !defined(__OpenBSD__) +#if !defined(_WIN64) && !defined(__APPLE__) && !defined(__OpenBSD__) cpu_set_t set; CPU_ZERO(&set); CPU_SET(core_id, &set); |