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author | Ramy Elgammal <ramy.elgammal@arm.com> | 2023-05-08 03:33:43 +0100 |
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committer | Ramy Elgammal <ramy.elgammal@arm.com> | 2023-05-10 12:16:01 +0000 |
commit | a8db612f4921ff606edb9891392d7f8ef94e22f3 (patch) | |
tree | f7791f9dacac7426b18bf69e134a5c7aea354f03 /src/cpu | |
parent | e9b3ee2badebf91188c1cd0e59d6aaa30ed60985 (diff) | |
download | ComputeLibrary-a8db612f4921ff606edb9891392d7f8ef94e22f3.tar.gz |
Re-enable dyanmic weights in Neon™ depthwise convolution
- Call Neon™ depthwise convolution validation inside in its configure() method.
Resolves: COMPMID-6188
Signed-off-by: Ramy Elgammal <ramy.elgammal@arm.com>
Change-Id: Ib2ae4d995ff2bbc92ce4496d4ab93cf09113e3e9
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9594
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Reviewed-by: Jakub Sujak <jakub.sujak@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/cpu')
-rw-r--r-- | src/cpu/kernels/pool2d/neon/fp32.cpp | 6 | ||||
-rw-r--r-- | src/cpu/operators/CpuDepthwiseConv2d.cpp | 12 |
2 files changed, 6 insertions, 12 deletions
diff --git a/src/cpu/kernels/pool2d/neon/fp32.cpp b/src/cpu/kernels/pool2d/neon/fp32.cpp index 8e93df3347..a400f3a95d 100644 --- a/src/cpu/kernels/pool2d/neon/fp32.cpp +++ b/src/cpu/kernels/pool2d/neon/fp32.cpp @@ -234,11 +234,9 @@ void poolingMxN_fp32_neon_nhwc_kernel_indices(const ITensor *src, ITensor *dst0, float res = min_value; uint32_t idx = 0U; const uint8_t *in_ptr_y = in_ptr_n + in_ptr_y_offset + in_ptr_x_offset; - uint32_t curr_kernel_index = pool_size_x * pool_start_y; for(int y = pool_start_y; y < pool_end_y; ++y) { const uint8_t *in_ptr_x = in_ptr_y + (x_off * sizeof(float)); - curr_kernel_index += pool_start_x; for(int x = pool_start_x; x < pool_end_x; ++x) { const float data = *(reinterpret_cast<const float *>(in_ptr_x)); @@ -248,9 +246,7 @@ void poolingMxN_fp32_neon_nhwc_kernel_indices(const ITensor *src, ITensor *dst0, res = data; } in_ptr_x += y_stride; - curr_kernel_index++; } - curr_kernel_index += (pool_size_x - pool_end_x); in_ptr_y += z_stride; } @@ -434,4 +430,4 @@ void poolingMxN_fp32_neon_nhwc(const ITensor *src, ITensor *dst0, ITensor *dst1, } } } // namespace cpu -} // namespace arm_compute
\ No newline at end of file +} // namespace arm_compute diff --git a/src/cpu/operators/CpuDepthwiseConv2d.cpp b/src/cpu/operators/CpuDepthwiseConv2d.cpp index ea451a461a..884fe5c4ed 100644 --- a/src/cpu/operators/CpuDepthwiseConv2d.cpp +++ b/src/cpu/operators/CpuDepthwiseConv2d.cpp @@ -83,11 +83,11 @@ void CpuDepthwiseConv2d::CpuDepthwiseConv2dOptimizedInternal::configure(ITensorI ARM_COMPUTE_ERROR_THROW_ON(CpuDepthwiseConv2dOptimizedInternal::validate(src, weights, (biases == nullptr) ? nullptr : biases, dst, info)); - _is_quantized = is_data_type_quantized_asymmetric(src->data_type()); - _has_bias = biases != nullptr; - _is_nchw = src->data_layout() == DataLayout::NCHW; - _permute = _is_nchw; - _is_prepared = false; + _is_quantized = is_data_type_quantized_asymmetric(src->data_type()); + _has_bias = biases != nullptr; + _is_nchw = src->data_layout() == DataLayout::NCHW; + _permute = _is_nchw; + _is_prepared = false; _are_weights_const = weights->are_values_constant(); // Configure pipeline @@ -461,8 +461,6 @@ void CpuDepthwiseConv2d::configure(ITensorInfo *src, const ITensorInfo *weights, Status CpuDepthwiseConv2d::validate(const ITensorInfo *src, const ITensorInfo *weights, const ITensorInfo *biases, const ITensorInfo *dst, const ConvolutionInfo &info) { - ARM_COMPUTE_RETURN_ERROR_ON_MSG(!weights->are_values_constant(), "Dynamic weights are not supported"); - DepthwiseConvolutionFunction depth_conv_func = get_depthwiseconvolution_function(src, weights, biases, dst, info); switch(depth_conv_func) { |