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author | Gunes Bayir <gunes.bayir@arm.com> | 2023-01-29 13:24:24 +0000 |
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committer | Gunes Bayir <gunes.bayir@arm.com> | 2023-02-01 09:59:30 +0000 |
commit | ae72a46e495742863dba44fcf5fdc673c9d2afbc (patch) | |
tree | 65bab43d0feddaa66b160ac7dc746651dc7c48de /src/cpu/operators | |
parent | ec320d9fc418e2d95a3a38ce87233397535f467d (diff) | |
download | ComputeLibrary-ae72a46e495742863dba44fcf5fdc673c9d2afbc.tar.gz |
Add new operator AddMulAdd for Neon™ backend for Float/Quantized types
This is a fused operator that merges Add + Mul + Add [+ Relu-based-Activation] layers and have an intermediate output after the first Add. It's supported for FP16/32/QASYMM8/QASYMM8_SIGNED data types.
The subsequent Add and Mul are intended for scaling and the coefficients only have one dimension (per channel).
The inputs are
- input1 : nD tensor [X, Y, Z, W, ..]
- input2 : nD tensor [X, Y, Z, W, ..]
- add_coef : 1D tensor [X]
- mul_coef : 1D tensor [X]
The outputs are
- out1 : nD tensor (intermediate output) [X, Y, Z, W, ..]
- out2 : nD tensor (final output) [X, Y, Z, W, ..]
The operation can be summarized as follows:
out1 <- input1 + input2
out2 <- Act(out1 * mul_coef + add_coef)
The activation function can be Identity, Relu, Bounded Relu or Lower/Upper Bounded Relu. The intermediate output can be skipped by providing a nullptr.
The reason of providing this operator is to be able to fuse in case of Residual network patterns and save computations by reducing memory back and forward.
Resolves: COMPMID-5463
Signed-off-by: Gunes Bayir <gunes.bayir@arm.com>
Change-Id: I8ef577aa623b036e9a9f655cc088493fd19a6109
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/9055
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Jakub Sujak <jakub.sujak@arm.com>
Reviewed-by: Viet-Hoa Do <viet-hoa.do@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Benchmark: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/cpu/operators')
-rw-r--r-- | src/cpu/operators/CpuAddMulAdd.cpp | 139 | ||||
-rw-r--r-- | src/cpu/operators/CpuAddMulAdd.h | 84 |
2 files changed, 223 insertions, 0 deletions
diff --git a/src/cpu/operators/CpuAddMulAdd.cpp b/src/cpu/operators/CpuAddMulAdd.cpp new file mode 100644 index 0000000000..3fd690e3f9 --- /dev/null +++ b/src/cpu/operators/CpuAddMulAdd.cpp @@ -0,0 +1,139 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#include "arm_compute/core/experimental/Types.h" +#include "arm_compute/runtime/NEON/NEScheduler.h" + +#include "src/common/utils/Log.h" +#include "src/core/helpers/MemoryHelpers.h" +#include "src/cpu/kernels/CpuAddMulAddKernel.h" +#include "src/cpu/operators/CpuAddMulAdd.h" +#include "src/cpu/utils/CpuAuxTensorHandler.h" + +namespace arm_compute +{ +namespace cpu +{ +void CpuAddMulAdd::configure(const ITensorInfo *input1, const ITensorInfo *input2, + const ITensorInfo *bn_mul, const ITensorInfo *bn_add, + ITensorInfo *add_output, ITensorInfo *final_output, + ConvertPolicy policy, const ActivationLayerInfo &act_info) +{ + ARM_COMPUTE_LOG_PARAMS(input1, input2, bn_mul, bn_add, add_output, final_output, policy, act_info); + + auto k = std::make_unique<kernels::CpuAddMulAddKernel>(); + + const DataType data_type = input1->data_type(); + if(is_data_type_quantized(data_type)) + { + _dequantize_bn_mul.configure(bn_mul, &_dequantized_bn_mul); + _dequantize_bn_add.configure(bn_add, &_dequantized_bn_add); + + k->configure(input1, input2, &_dequantized_bn_mul, &_dequantized_bn_add, add_output, final_output, policy, act_info); + + // Save auxilary memory requirements after configuration + _aux_mem[DequantizedBnMul] = experimental::MemoryInfo(offset_int_vec(DequantizedBnMul), experimental::MemoryLifetime::Temporary, _dequantized_bn_mul.total_size()); + _aux_mem[DequantizedBnAdd] = experimental::MemoryInfo(offset_int_vec(DequantizedBnAdd), experimental::MemoryLifetime::Temporary, _dequantized_bn_add.total_size()); + } + else + { + k->configure(input1, input2, bn_mul, bn_add, add_output, final_output, policy, act_info); + } + + _kernel = std::move(k); +} + +Status CpuAddMulAdd::validate(const ITensorInfo *input1, const ITensorInfo *input2, + const ITensorInfo *bn_mul, const ITensorInfo *bn_add, + const ITensorInfo *add_output, const ITensorInfo *final_output, + ConvertPolicy policy, const ActivationLayerInfo &act_info) +{ + const DataType data_type = input1->data_type(); + if(is_data_type_quantized(data_type)) + { + TensorInfo dequantized_bn_mul; + TensorInfo dequantized_bn_add; + + ARM_COMPUTE_RETURN_ON_ERROR(CpuDequantize::validate(bn_mul, &dequantized_bn_mul)); + ARM_COMPUTE_RETURN_ON_ERROR(CpuDequantize::validate(bn_add, &dequantized_bn_add)); + + return kernels::CpuAddMulAddKernel::validate(input1, input2, &dequantized_bn_mul, &dequantized_bn_add, add_output, final_output, policy, act_info); + } + else + { + return kernels::CpuAddMulAddKernel::validate(input1, input2, bn_mul, bn_add, add_output, final_output, policy, act_info); + } +} + +void CpuAddMulAdd::run(ITensorPack &tensors) +{ + const DataType data_type = tensors.get_const_tensor(TensorType::ACL_SRC_0)->info()->data_type(); + + if(is_data_type_quantized(data_type)) + { + const ITensor *bn_mul = tensors.get_const_tensor(TensorType::ACL_SRC_2); + const ITensor *bn_add = tensors.get_const_tensor(TensorType::ACL_SRC_3); + + CpuAuxTensorHandler dequantized_bn_mul_handler(offset_int_vec(DequantizedBnMul), _dequantized_bn_mul, tensors, true); + CpuAuxTensorHandler dequantized_bn_add_handler(offset_int_vec(DequantizedBnAdd), _dequantized_bn_add, tensors, true); + + ITensorPack dequantize_mul_pack = + { + { TensorType::ACL_SRC_0, bn_mul }, + { TensorType::ACL_DST_0, dequantized_bn_mul_handler.get() } + }; + + ITensorPack dequantize_add_pack = + { + { TensorType::ACL_SRC_0, bn_add }, + { TensorType::ACL_DST_0, dequantized_bn_add_handler.get() } + }; + + _dequantize_bn_mul.run(dequantize_mul_pack); + _dequantize_bn_add.run(dequantize_add_pack); + + ITensorPack add_mul_add_pack = + { + { TensorType::ACL_SRC_0, tensors.get_const_tensor(TensorType::ACL_SRC_0) }, + { TensorType::ACL_SRC_1, tensors.get_const_tensor(TensorType::ACL_SRC_1) }, + { TensorType::ACL_SRC_2, dequantized_bn_mul_handler.get() }, + { TensorType::ACL_SRC_3, dequantized_bn_add_handler.get() }, + { TensorType::ACL_DST_0, tensors.get_tensor(TensorType::ACL_DST_0) }, + { TensorType::ACL_DST_1, tensors.get_tensor(TensorType::ACL_DST_1) }, + }; + + NEScheduler::get().schedule_op(_kernel.get(), Window::DimY, _kernel->window(), add_mul_add_pack); + } + else + { + NEScheduler::get().schedule_op(_kernel.get(), Window::DimY, _kernel->window(), tensors); + } +} + +experimental::MemoryRequirements CpuAddMulAdd::workspace() const +{ + return _aux_mem; +} + +} // namespace cpu +} // namespace arm_compute diff --git a/src/cpu/operators/CpuAddMulAdd.h b/src/cpu/operators/CpuAddMulAdd.h new file mode 100644 index 0000000000..cf1ece68f1 --- /dev/null +++ b/src/cpu/operators/CpuAddMulAdd.h @@ -0,0 +1,84 @@ +/* + * Copyright (c) 2023 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ +#ifndef SRC_CPU_OPERATORS_CPUADDMULADD +#define SRC_CPU_OPERATORS_CPUADDMULADD + +#include "arm_compute/core/TensorInfo.h" + +#include "src/cpu/ICpuOperator.h" +#include "src/cpu/operators/CpuDequantize.h" + +namespace arm_compute +{ +namespace cpu +{ +/** Basic function to run @ref kernels::CpuAddMulAddKernel */ +class CpuAddMulAdd : public ICpuOperator +{ +public: + /** Initialize the operator's inputs and outputs. + * + * Similar to @ref NEAddMulAdd::configure() + * + */ + void configure(const ITensorInfo *input1, const ITensorInfo *input2, + const ITensorInfo *bn_mul, const ITensorInfo *bn_add, + ITensorInfo *add_output, ITensorInfo *final_output, + ConvertPolicy policy, const ActivationLayerInfo &act_info); + /** Static function to check if given info will lead to a valid configuration + * + * Similar to @ref CpuAddMulAdd::configure() + * + * @return a status + */ + static Status validate(const ITensorInfo *input1, const ITensorInfo *input2, + const ITensorInfo *bn_mul, const ITensorInfo *bn_add, + const ITensorInfo *add_output, const ITensorInfo *final_output, + ConvertPolicy policy, const ActivationLayerInfo &act_info); + + // Inherited methods overridden: + void run(ITensorPack &tensors) override; + + // We need auxilary memory to dequantize batchnorm coefficients + experimental::MemoryRequirements workspace() const override; + +private: + enum AuxTensorIdx + { + DequantizedBnMul = 0, + DequantizedBnAdd, + Count + }; + + CpuDequantize _dequantize_bn_mul{}; + CpuDequantize _dequantize_bn_add{}; + + TensorInfo _dequantized_bn_mul{}; + TensorInfo _dequantized_bn_add{}; + + experimental::MemoryRequirements _aux_mem{ Count }; +}; +} // namespace cpu +} // namespace arm_compute +#endif /* SRC_CPU_OPERATORS_CPUADDMULADD */ |