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| author | Dana Zlotnik <dana.zlotnik@arm.com> | 2021-11-15 08:46:04 +0200 |
|---|---|---|
| committer | Dana Zlotnik <dana.zlotnik@arm.com> | 2021-11-28 05:58:11 +0000 |
| commit | bd2942d7c701a664421ce8ef7145f97b7163201a (patch) | |
| tree | 54b2da1443e96886535173a5350199dfdddc0647 /src/core/common/Registrars.h | |
| parent | dc2282f40b40c0d85b113c792f90d1faa2759f46 (diff) | |
| download | ComputeLibrary-bd2942d7c701a664421ce8ef7145f97b7163201a.tar.gz | |
Decouple CpuAddKernel
1- NEON supported data types are : fp32, fp16, u8, s16, s32 , q8, q_s8 , q16
2- SVE supported data types are: fp32, fp16, u8, s16, s32
3- SVE2 supported data types are : q8, q_s8 , q16
4- Re-arange SVE folder sturct
** Need to remove gaurds and add testing after Multi ISA build system and validation tests will be avalible
Resolves COMPMID-4635
Change-Id: I90e4f6a219478aa9ad5c4a6b9858496afa8af42d
Signed-off-by: Dana Zlotnik <dana.zlotnik@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/6711
Comments-Addressed: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Giorgio Arena <giorgio.arena@arm.com>
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Diffstat (limited to 'src/core/common/Registrars.h')
| -rw-r--r-- | src/core/common/Registrars.h | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/core/common/Registrars.h b/src/core/common/Registrars.h index 65f6c7093d..c7fbf7f831 100644 --- a/src/core/common/Registrars.h +++ b/src/core/common/Registrars.h @@ -32,6 +32,12 @@ #define REGISTER_FP16_SVE(func_name) nullptr #endif /* defined(ARM_COMPUTE_ENABLE_SVE) */ +#if defined(ARM_COMPUTE_ENABLE_SVE2) +#define REGISTER_FP16_SVE2(func_name) &(func_name) +#else /* !defined(ARM_COMPUTE_ENABLE_SVE2) */ +#define REGISTER_FP16_SVE2(func_name) nullptr +#endif /* defined(ARM_COMPUTE_ENABLE_SVE2) */ + #if defined(ARM_COMPUTE_ENABLE_NEON) && defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) #define REGISTER_FP16_NEON(func_name) &(func_name) #else /* !defined(ARM_COMPUTE_ENABLE_NEON) */ @@ -41,6 +47,7 @@ #else /* !defined(ENABLE_FP16_KERNELS) */ #define REGISTER_FP16_NEON(func_name) nullptr #define REGISTER_FP16_SVE(func_name) nullptr +#define REGISTER_FP16_SVE2(func_name) nullptr #endif /* defined(__ARM_FEATURE_FP16_VECTOR_ARITHMETIC) && defined(ENABLE_FP16_KERNELS) */ #if defined(ENABLE_FP32_KERNELS) @@ -51,6 +58,12 @@ #define REGISTER_FP32_SVE(func_name) nullptr #endif /* defined(ARM_COMPUTE_ENABLE_SVE) */ +#if defined(ARM_COMPUTE_ENABLE_SVE2) +#define REGISTER_FP32_SVE2(func_name) &(func_name) +#else /* !defined(ARM_COMPUTE_ENABLE_SVE2) */ +#define REGISTER_FP32_SVE2(func_name) nullptr +#endif /* defined(ARM_COMPUTE_ENABLE_SVE2) */ + #if defined(ARM_COMPUTE_ENABLE_NEON) #define REGISTER_FP32_NEON(func_name) &(func_name) #else /* !defined(ARM_COMPUTE_ENABLE_NEON) */ @@ -60,6 +73,7 @@ #else /* defined(ENABLE_FP32_KERNELS) */ #define REGISTER_FP32_NEON(func_name) nullptr #define REGISTER_FP32_SVE(func_name) nullptr +#define REGISTER_FP32_SVE2(func_name) nullptr #endif /* defined(ENABLE_FP32_KERNELS) */ #if defined(ENABLE_QASYMM8_SIGNED_KERNELS) @@ -72,9 +86,16 @@ #define REGISTER_QASYMM8_SIGNED_SVE(func_name) nullptr #endif /* defined(ARM_COMPUTE_ENABLE_SVE) */ +#if defined(ARM_COMPUTE_ENABLE_SVE2) +#define REGISTER_QASYMM8_SIGNED_SVE2(func_name) &(func_name) +#else /* !defined(ARM_COMPUTE_ENABLE_SVE2) */ +#define REGISTER_QASYMM8_SIGNED_SVE2(func_name) nullptr +#endif /* defined(ARM_COMPUTE_ENABLE_SVE2) */ + #else /* defined(ENABLE_QASYMM8_SIGNED_KERNELS) */ #define REGISTER_QASYMM8_SIGNED_NEON(func_name) nullptr #define REGISTER_QASYMM8_SIGNED_SVE(func_name) nullptr +#define REGISTER_QASYMM8_SIGNED_SVE2(func_name) nullptr #endif /* defined(ENABLE_QASYMM8_SIGNED_KERNELS) */ #if defined(ENABLE_QASYMM8_KERNELS) @@ -86,9 +107,16 @@ #define REGISTER_QASYMM8_SVE(func_name) nullptr #endif /* defined(ARM_COMPUTE_ENABLE_SVE) */ +#if defined(ARM_COMPUTE_ENABLE_SVE2) +#define REGISTER_QASYMM8_SVE2(func_name) &(func_name) +#else /* !defined(ARM_COMPUTE_ENABLE_SVE2) */ +#define REGISTER_QASYMM8_SVE2(func_name) nullptr +#endif /* defined(ARM_COMPUTE_ENABLE_SVE2) */ + #else /* defined(ENABLE_QASYMM8_KERNELS) */ #define REGISTER_QASYMM8_NEON(func_name) nullptr #define REGISTER_QASYMM8_SVE(func_name) nullptr +#define REGISTER_QASYMM8_SVE2(func_name) nullptr #endif /* defined(ENABLE_QASYMM8_KERNELS) */ #if defined(ENABLE_QSYMM16_KERNELS) @@ -101,9 +129,16 @@ #define REGISTER_QSYMM16_SVE(func_name) nullptr #endif /* defined(ARM_COMPUTE_ENABLE_SVE) */ +#if defined(ARM_COMPUTE_ENABLE_SVE2) +#define REGISTER_QSYMM16_SVE2(func_name) &(func_name) +#else /* !defined(ARM_COMPUTE_ENABLE_SVE2) */ +#define REGISTER_QSYMM16_SVE2(func_name) nullptr +#endif /* defined(ARM_COMPUTE_ENABLE_SVE2) */ + #else /* defined(ENABLE_QSYMM16_KERNELS) */ #define REGISTER_QSYMM16_NEON(func_name) nullptr #define REGISTER_QSYMM16_SVE(func_name) nullptr +#define REGISTER_QSYMM16_SVE2(func_name) nullptr #endif /* defined(ENABLE_QSYMM16_KERNELS) */ #if defined(ENABLE_INTEGER_KERNELS) @@ -114,6 +149,12 @@ #define REGISTER_INTEGER_SVE(func_name) nullptr #endif /* defined(ARM_COMPUTE_ENABLE_SVE) */ +#if defined(ARM_COMPUTE_ENABLE_SVE2) +#define REGISTER_INTEGER_SVE2(func_name) &(func_name) +#else /* !defined(ARM_COMPUTE_ENABLE_SVE2) */ +#define REGISTER_INTEGER_SVE2(func_name) nullptr +#endif /* defined(ARM_COMPUTE_ENABLE_SVE2) */ + #if defined(ARM_COMPUTE_ENABLE_NEON) #define REGISTER_INTEGER_NEON(func_name) &(func_name) #else /* !defined(ARM_COMPUTE_ENABLE_NEON) */ @@ -123,6 +164,7 @@ #else /* defined(ENABLE_INTEGER_KERNELS) */ #define REGISTER_INTEGER_NEON(func_name) nullptr #define REGISTER_INTEGER_SVE(func_name) nullptr +#define REGISTER_INTEGER_SVE2(func_name) nullptr #endif /* defined(ENABLE_INTEGER_KERNELS) */ #endif /* SRC_CORE_COMMON_REGISTRARS_H */ |