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author | Michele Di Giorgio <michele.digiorgio@arm.com> | 2021-01-22 09:47:04 +0000 |
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committer | Michele Di Giorgio <michele.digiorgio@arm.com> | 2021-06-18 10:33:48 +0000 |
commit | d02d5edfa15ba6c04a9986a8a362a945cb38ac31 (patch) | |
tree | ced4f49691d6c7038e347a8709b315bff59c64cf /src/core/NEON/kernels/arm_conv/depthwise/interleaves/list.hpp | |
parent | b014c27ba6db9840e4a72519760d51a87a2af7e7 (diff) | |
download | ComputeLibrary-d02d5edfa15ba6c04a9986a8a362a945cb38ac31.tar.gz |
Integrate improved CPU depthwise convolution kernels
* Replace assembly kernels for depthwise convolution with more optimized
ones.
* Add int8 assembly kernels.
* Fix implicit padding on optimized kernels
Resolves: COMPMID-3867, COMPMID-4361
Change-Id: I0b0867e05f61be4f368f62190d55e14d0ab3ebf2
Signed-off-by: Michele Di Giorgio <michele.digiorgio@arm.com>
Reviewed-on: https://review.mlplatform.org/c/ml/ComputeLibrary/+/5622
Tested-by: Arm Jenkins <bsgcomp@arm.com>
Reviewed-by: Georgios Pinitas <georgios.pinitas@arm.com>
Diffstat (limited to 'src/core/NEON/kernels/arm_conv/depthwise/interleaves/list.hpp')
-rw-r--r-- | src/core/NEON/kernels/arm_conv/depthwise/interleaves/list.hpp | 119 |
1 files changed, 119 insertions, 0 deletions
diff --git a/src/core/NEON/kernels/arm_conv/depthwise/interleaves/list.hpp b/src/core/NEON/kernels/arm_conv/depthwise/interleaves/list.hpp new file mode 100644 index 0000000000..41f0495acf --- /dev/null +++ b/src/core/NEON/kernels/arm_conv/depthwise/interleaves/list.hpp @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2021 Arm Limited. + * + * SPDX-License-Identifier: MIT + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to + * deal in the Software without restriction, including without limitation the + * rights to use, copy, modify, merge, publish, distribute, sublicense, and/or + * sell copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE + * SOFTWARE. + */ + +#pragma once + +namespace arm_conv { +namespace depthwise { + +#if defined(__ARM_FEATURE_SVE) + +class interleave_sve_u8q_3x3_dot +{ + public: + static void pack_parameters(unsigned int, void *, const int32_t *, const uint8_t *, const arm_gemm::Requantize32 &, size_t, size_t); + static size_t get_packed_size(const DepthwiseArgs &); +}; + +class interleave_sve_s8q_3x3_dot +{ + public: + static void pack_parameters(unsigned int, void *, const int32_t *, const int8_t *, const arm_gemm::Requantize32 &, size_t, size_t); + static size_t get_packed_size(const DepthwiseArgs &); +}; + +class interleave_sve_u8q_3x3_mla +{ + public: + static void pack_parameters(unsigned int, void *, const uint8_t *, size_t, size_t); + static size_t get_packed_size(const DepthwiseArgs &); +}; + +class interleave_sve_s8q_3x3_mla +{ + public: + static void pack_parameters(unsigned int, void *, const int8_t *, size_t, size_t); + static size_t get_packed_size(const DepthwiseArgs &); +}; + +class interleave_sve_u8q_5x5_mla +{ + public: + static void pack_parameters(unsigned int, void *, const uint8_t *, size_t, size_t); + static size_t get_packed_size(const DepthwiseArgs &); +}; + +class interleave_sve_s8q_5x5_mla +{ + public: + static void pack_parameters(unsigned int, void *, const int8_t *, size_t, size_t); + static size_t get_packed_size(const DepthwiseArgs &); +}; + +#endif // defined(__ARM_FEATURE_SVE) + +class interleave_a64_u8q_3x3_dot +{ + public: + static void pack_parameters(unsigned int, void *, const int32_t *, const uint8_t *, const arm_gemm::Requantize32 &, size_t, size_t); + static size_t get_packed_size(const DepthwiseArgs &); +}; + +class interleave_a64_s8q_3x3_dot +{ + public: + static void pack_parameters(unsigned int, void *, const int32_t *, const int8_t *, const arm_gemm::Requantize32 &, size_t, size_t); + static size_t get_packed_size(const DepthwiseArgs &); +}; + +class interleave_a64_u8q_3x3_mla +{ + public: + static void pack_parameters(unsigned int, void *, const uint8_t *, size_t, size_t); + static size_t get_packed_size(const DepthwiseArgs &); +}; + +class interleave_a64_s8q_3x3_mla +{ + public: + static void pack_parameters(unsigned int, void *, const int8_t *, size_t, size_t); + static size_t get_packed_size(const DepthwiseArgs &); +}; + +class interleave_a64_u8q_5x5_mla +{ + public: + static void pack_parameters(unsigned int, void *, const uint8_t *, size_t, size_t); + static size_t get_packed_size(const DepthwiseArgs &); +}; + +class interleave_a64_s8q_5x5_mla +{ + public: + static void pack_parameters(unsigned int, void *, const int8_t *, size_t, size_t); + static size_t get_packed_size(const DepthwiseArgs &); +}; + +} // namespace depthwise +} // namespace arm_conv |